Adding hardware dispatcher

src/verilog/rtl/Makefile

@@ -17,6 +17,7 @@ build:
 	cd simf && make my_build
 	cd rfa && make my_build
 	cd alu && make my_build
+	cd dispatcher && make my_build
 
 fpga: build
 	mkdir -p fpga_core
@@ -34,7 +35,7 @@ fpga: build
 	cp simf/build/* fpga_core/
 	cp rfa/build/* fpga_core/
 	cp alu/build/* fpga_core/
-  cp fpga/* fpga_core/
+	cp fpga/* fpga_core/
 
 compile: build
 	vcs -full64 +libext+.v compute_unit/build/*.v decode/build/*.v exec/build/*.v fetch/build/*.v instr_buffer/build/*.v issue/build/*.v lsu/build/*.v memory/build/*.v salu/build/*.v sgpr/build/*.v simd/build/*.v tracemon/build/*.v tracemon/*.c vgpr/build/*.v wavepool/build/*.v -y common/build/ +lint=all -timescale=1ns/1ns -l compile.log -debug_all +v2k -sverilog
@@ -94,6 +95,7 @@ uncheck:
 	cd wavepool && make clean
 	cd simf && make clean
 	cd rfa && make clean
+	cd dispatcher && make clean
 	#cd alu && make clean
 
 clean: unbuild uncheck

src/verilog/rtl/dispatcher/.gitignore

@@ -0,0 +1,29 @@
+# ignore ModelSim generated files and directories (temp files and so on)
+[_@]*
+
+# ignore compilation output of ModelSim
+*.prw
+*.mti
+*.dat
+*.dbs
+*.psm
+*.bak
+*.cmp
+*.jpg
+*.html
+*.bsf
+
+# ignore simulation output of ModelSim
+wlf*
+*.wlf
+*.vstf
+*.ucdb
+cov*/
+transcript*
+sc_dpiheader.h
+vsim.dbg
+
+# Emacs crap
+*~
+\#*\#
+.#*

src/verilog/rtl/dispatcher/Makefile

@@ -0,0 +1,11 @@
+#This Makefile supports the following commands:
+#make build
+#make clean
+#make unbuild (same as clean)
+
+include ../../make/rtl.mk
+clean: unbuild
+	rm -rf csrc/ simv simv.daidir/ compile.log
+
+compile: build
+	vcs -full64 +libext+.v build/*.v -y ../common/build/ +lint=all -timescale=1ns/1ns -l compile.log -debug_all +v2k