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i32x4.dot_i16x8_s instruction #127

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Oct 19, 2020
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i32x4.dot_i16x8_s instruction #127

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i32x4.dot_i16x8_s instruction
Maratyszcza Jun 2, 2020
95e2d31
Update proposals/simd/ImplementationStatus.md
Maratyszcza Oct 6, 2020
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1 change: 1 addition & 0 deletions proposals/simd/BinarySIMD.md
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Original file line number Diff line number Diff line change
Expand Up @@ -181,6 +181,7 @@ For example, `ImmLaneIdx16` is a byte with values in the range 0-15 (inclusive).
| `i32x4.min_u` | `0xb7`| - |
| `i32x4.max_s` | `0xb8`| - |
| `i32x4.max_u` | `0xb9`| - |
| `i32x4.dot_i16x8_s` | `0xba`| - |
| `i64x2.neg` | `0xc1`| - |
| `i64x2.shl` | `0xcb`| - |
| `i64x2.shr_s` | `0xcc`| - |
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1 change: 1 addition & 0 deletions proposals/simd/ImplementationStatus.md
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Expand Up @@ -149,6 +149,7 @@
| `i32x4.min_u` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `i32x4.max_s` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `i32x4.max_u` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `i32x4.dot_i16x8_s` | | | | | |
| `i64x2.neg` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `i64x2.shl` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `i64x2.shr_s` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
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4 changes: 2 additions & 2 deletions proposals/simd/NewOpcodes.md
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Expand Up @@ -98,13 +98,13 @@
| i8x16.sub | 0x71 | i16x8.sub | 0x91 | i32x4.sub | 0xb1 | i64x2.sub | 0xd1 |
| i8x16.sub_sat_s | 0x72 | i16x8.sub_sat_s | 0x92 | ---- sub_sat ---- | 0xb2 | ---- | 0xd2 |
| i8x16.sub_sat_u | 0x73 | i16x8.sub_sat_u | 0x93 | ---- sub_sat ---- | 0xb3 | ---- | 0xd3 |
| ---- dot ---- | 0x74 | ---- dot ---- | 0x94 | ---- dot ---- | 0xb4 | ---- | 0xd4 |
| ------------- | 0x74 | ------------- | 0x94 | ------------- | 0xb4 | ---- | 0xd4 |
| ---- mul ---- | 0x75 | i16x8.mul | 0x95 | i32x4.mul | 0xb5 | i64x2.mul | 0xd5 |
| i8x16.min_s | 0x76 | i16x8.min_s | 0x96 | i32x4.min_s | 0xb6 | ---- | 0xd6 |
| i8x16.min_u | 0x77 | i16x8.min_u | 0x97 | i32x4.min_u | 0xb7 | ---- | 0xd7 |
| i8x16.max_s | 0x78 | i16x8.max_s | 0x98 | i32x4.max_s | 0xb8 | ---- | 0xd8 |
| i8x16.max_u | 0x79 | i16x8.max_u | 0x99 | i32x4.max_u | 0xb9 | ---- | 0xd9 |
| ---- avgr_s ---- | 0x7a | ---- avgr_s ---- | 0x9a | ---- avgr_s ---- | 0xba | ---- | 0xda |
| ---------------- | 0x7a | ---------------- | 0x9a | i32x4.dot_i16x8_s | 0xba | ---- | 0xda |
| i8x16.avgr_u | 0x7b | i16x8.avgr_u | 0x9b | ---- avgr_u ---- | 0xbb | ---- | 0xdb |

| f32x4 Op | opcode | f64x2 Op | opcode |
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5 changes: 5 additions & 0 deletions proposals/simd/SIMD.md
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Expand Up @@ -395,6 +395,11 @@ def S.mul(a, b):
return S.lanewise_binary(mul, a, b)
```

### Integer dot product
* `i32x4.dot_i16x8_s(a: v128, b: v128) -> v128`

Lane-wise multiply signed 16-bit integers in the two input vectors and add adjacent pairs of the full 32-bit results.

### Integer negation
* `i8x16.neg(a: v128) -> v128`
* `i16x8.neg(a: v128) -> v128`
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