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[spectext] Load lane and store lane validation and semantics #445
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Load lane and store lane instructions added in WebAssembly#350.
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I think |
rossberg
approved these changes
Feb 4, 2021
| \K{v128.}\STORE\K{8\_lane}~\memarg ~|~ | ||
| \K{v128.}\STORE\K{16\_lane}~\memarg \\&&|& | ||
| \K{v128.}\STORE\K{32\_lane}~\memarg ~|~ | ||
| \K{v128.}\STORE\K{64\_lane}~\memarg \\&&|& |
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Can we avoid all the repetition (including splat) by defining an auxiliary lanewidth non-terminal?
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Good idea, it does look a tiny bit squished up:
(Also made a fix to the load/store lane instructions, they take a \laneidx immediate after the \memarg.
rossberg
approved these changes
Feb 9, 2021
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Load lane and store lane instructions added in #350.