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Add Hybrid Updating Strategy (HUS) #1043

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merged 10 commits into from
Aug 14, 2024
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diriLin
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@diriLin diriLin commented Aug 2, 2024

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@eddieh-xlnx
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eddieh-xlnx commented Aug 2, 2024

This PR brings in the Hybrid Updating Strategy technique as described in:

@inproceedings{zang2024parallel,
  title={An Open-Source Fast Parallel Routing Approach for Commercial FPGAs},
  author={Zang, Xinshi and Lin, Wenhao and Lin, Shiju and Liu, Jinwei and Young, Evangeline FY},
  booktitle={Proceedings of the Great Lakes Symposium on VLSI 2024},
  year={2024}
}

Currently, this strategy is disabled by default and can be enabled using the --hus parameter, with further parameters to tune its behaviour.

In a nutshell, this technique reduces the growth of used nodes' present cost and instead increases the growth of overused nodes' historical cost --- with a view to reducing the runtime required to resolve conflicts in particularly congested designs --- once a number of thresholds relating to the number of congested connections and congested nodes are met.

On the 28 FPGA24 Routing Contest benchmarks, 7 of them triggered the threshold for HUS to activate (the rest are unaffected).

Summary is (geomean values):

  • Non timing driven: 57% end-to-end wall time improvement
  • Timing driven: 28% end-to-end wall time improvement, 15% critical path delay improvement

Data:

Wall time (non timing driven)  Baseline --hus Speedup
boom_med_pb 250.27 214.62 1.17
boom_soc 1392.01 1330.72 1.05
boom_soc_v2 5249 2219.67 2.36
mlcad_d181 4309 1383.67 3.11
mlcad_d181_lefttwo3rds 1896.25 819.81 2.31
rapidwright_picoblazearray 195.81 200.81 0.98
vtr_mcml 270.5 232.44 1.16
Geomean      1.57
Wall time (timing driven)  Baseline --hus Speedup
boom_med_pb 286.29 266.44 1.07
boom_soc 4057 4149 0.98
boom_soc_v2 6410 4560 1.41
mlcad_d181 4870 1977.61 2.46
mlcad_d181_lefttwo3rds 2293.41 1329.57 1.72
rapidwright_picoblazearray 283.43 328.71 0.86
vtr_mcml 343.94 336.91 1.02
Geomean      1.28
Critical path delay* (timing driven) Baseline --hus Improvement
boom_med_pb 11038 9208 1.20
boom_soc 22282 20170 1.10
boom_soc_v2 15504 11982 1.29
mlcad_d181 9760 8317 1.17
mlcad_d181_lefttwo3rds 8667 7722 1.12
rapidwright_picoblazearray 3108 2796 1.11
vtr_mcml 8977 8323 1.08
Geomean      1.15

(* with timing closure guarantee value)

@eddieh-xlnx eddieh-xlnx merged commit 63c8bd1 into Xilinx:master Aug 14, 2024
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3 participants