make synth stuck at synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_args

[janboeye]

Version

Yosys 0.45 (git sha1 3e0dc2f, clang++ 14.0.0-1ubuntu1 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

pull the my branch of https://github.com/janboeye/OpenROAD-flow-scripts.

execute make synth

Expected Behavior

finish the synthesis without any error

Actual Behavior

when I synthesis Xiangshan which is a big riscv cpu, it stuck at the second round yosys synth command
synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_args
at stage
5.3.1. Executing OPT_EXPR pass (perform const folding).

[janboeye]

I encountered another problem.
[114278.133373] ERROR: Assert `port.en == State::S1' failed in kernel/mem.cc:469.
1_1_yosys.log

Does this mean Verilog code contain any design errors? If so, how can I identify where the errors are?

Thanks a lot!

[povik]

@janboeye Hello, can you post reproduction steps for this second issue?

[povik]

To answer your question, it could be there’s a design error, but even if there is, there’s a Yosys bug as you are seeing an internal Yosys error.