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444 Open 1,293 Closed
444 Open 1,293 Closed
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Issues list

Any link_design equivalent or alternative? pending-verification This issue is pending verification and/or reproduction
#4660 opened Oct 12, 2024 by redpanda3
Verilog globals appended to modules instead of prepended pending-verification This issue is pending verification and/or reproduction
#4653 opened Oct 10, 2024 by jmi2k
1
4
dfflibmap: support flops with enable feature-request
#4652 opened Oct 10, 2024 by Ravenslofty
@Ravenslofty
FSM pass equivalence bug pending-verification This issue is pending verification and/or reproduction
#4651 opened Oct 10, 2024 by joonho3020
sta command hangs on some designs pending-verification This issue is pending verification and/or reproduction
#4648 opened Oct 9, 2024 by lukbau
write_btor: Part selects of undriven signals are lowered as separate inputs pending-verification This issue is pending verification and/or reproduction
#4640 opened Oct 8, 2024 by georgerennie
1
Co-simulation fails for $fa cell pending-verification This issue is pending verification and/or reproduction
#4638 opened Oct 7, 2024 by RCoeurjoly
7
tee -q -o <bad-path> fails silently pending-verification This issue is pending verification and/or reproduction
#4636 opened Oct 7, 2024 by povik
make synth stuck at synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_args pending-verification This issue is pending verification and/or reproduction
#4634 opened Oct 7, 2024 by janboeye
3
log_deprecated feature-request
#4623 opened Oct 1, 2024 by widlarizer
abc segfaults in certain usecase ABC bug
#4622 opened Oct 1, 2024 by MrHighVoltage
2
Synthesis fails on MacOS but succeeds on Linux (possibly ABC error) pending-verification This issue is pending verification and/or reproduction
#4618 opened Sep 29, 2024 by agrif
2
VCD file parsing error in sim pass with GHDL-generated VCDs due to whitespace handling pending-verification This issue is pending verification and/or reproduction
#4617 opened Sep 27, 2024 by RCoeurjoly
1
Efficient handling of patterns emitted by sv2v feature-request
#4615 opened Sep 26, 2024 by povik
7
Yosys Synthesis Fails with std::out_of_range Error in OPT_DEMORGAN Pass pending-verification This issue is pending verification and/or reproduction
#4610 opened Sep 24, 2024 by LoSyTe
1
5
Nanoxplore synthesis does not works when using abc9 flow pending-verification This issue is pending verification and/or reproduction
#4606 opened Sep 19, 2024 by samhanic
1
Importing init of memory is extremely slow bug regression
#4601 opened Sep 17, 2024 by marzoul
1
Port names starting with '%' cause stack buffer overflow during error reporting pending-verification This issue is pending verification and/or reproduction
#4599 opened Sep 13, 2024 by mattyoung101
2
Excessive recursion in simple program bug
#4598 opened Sep 12, 2024 by joaovam
2
verific: wrong source attribute for $add cell with binary literal operand pending-verification This issue is pending verification and/or reproduction
#4597 opened Sep 12, 2024 by RCoeurjoly
@mmicko
Inconsistency with how libyosys is imported in Python feature-request
#4591 opened Sep 9, 2024 by donn
Synthesis with synth_xilinx crashes in TECHMAP pass pending-verification This issue is pending verification and/or reproduction
#4590 opened Sep 9, 2024 by marzoul
2
Github tag style feature-request
#4586 opened Sep 7, 2024 by hpretl
5
Get a proper command line parser feature-request
#4580 opened Sep 4, 2024 by widlarizer
@widlarizer
1
New $check flavors: warning and error feature-request
#4575 opened Aug 30, 2024 by povik
3
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