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1. General-Slow-DDR3-Interface General-Slow-DDR3-Interface Public

   A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.

   Verilog 36 9

2. LicheeTang20K_DDR_Test LicheeTang20K_DDR_Test Public

   The DDR Test Firmware for LicheeTang20K.

   Verilog 16 3

3. USB_Clock_Generator USB_Clock_Generator Public

   A Clock Generator with USB Type-C, based on CH551 and MS5351 (Compatible with Si5351)

   C 2 1

4. verilog_UDP verilog_UDP Public

   SystemVerilog 6 1