Rename HXT100G to HTG-640

Signed-off-by: Alex Forencich <[email protected]>
alexforencich · Jul 22, 2023 · b1177eb · b1177eb
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Showing 39 changed files with 6 additions and 6 deletions.
diff --git a/README.md b/README.md
@@ -46,7 +46,7 @@ following boards:
 *  Exablaze ExaNIC X10 (Xilinx Kintex UltraScale XCKU035)
 *  Exablaze ExaNIC X25 (Xilinx Kintex UltraScale+ XCKU3P)
 *  HiTech Global HTG-9200 (Xilinx UltraScale+ XCVU9P)
-*  HiTech Global HTG-V6HXT-100GIG-565 (Xilinx Virtex 6 XC6VHX565T)
+*  HiTech Global HTG-640 (HTG-V6HXT-100GIG-565) (Xilinx Virtex 6 XC6VHX565T)
 *  Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P)
 *  Xilinx KC705 (Xilinx Kintex 7 XC7K325T)
 *  Xilinx ML605 (Xilinx Virtex 6 XC6VLX240T)

diff --git a/example/HXT100G/fpga/Makefile → example/HTG640/fpga/Makefile b/example/HXT100G/fpga/Makefile → example/HTG640/fpga/Makefile
diff --git a/example/HXT100G/fpga/README.md → example/HTG640/fpga/README.md b/example/HXT100G/fpga/README.md → example/HTG640/fpga/README.md
@@ -1,8 +1,8 @@
-# Verilog Ethernet HXT100G Example Design
+# Verilog Ethernet HTG-640 Example Design
 
 ## Introduction
 
-This example design targets the HiTech Global HXT100G FPGA board.
+This example design targets the HiTech Global HTG-640 (HTG-V6HXT-100GIG-565) FPGA board.
 
 The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
 will echo back any packets received.  The design will also respond correctly
@@ -18,7 +18,7 @@ in PATH.
 
 ## How to test
 
-Run make program to program the HXT100G board with the Xilinx Impact software.
+Run make program to program the HTG-640 board with the Xilinx Impact software.
 Then run
 
     netcat -u 192.168.1.128 1234

diff --git a/example/HXT100G/fpga/common/xilinx.mk → example/HTG640/fpga/common/xilinx.mk b/example/HXT100G/fpga/common/xilinx.mk → example/HTG640/fpga/common/xilinx.mk
diff --git a/example/HXT100G/fpga/coregen/Makefile → example/HTG640/fpga/coregen/Makefile b/example/HXT100G/fpga/coregen/Makefile → example/HTG640/fpga/coregen/Makefile
diff --git a/example/HXT100G/fpga/coregen/coregen.cgp → example/HTG640/fpga/coregen/coregen.cgp b/example/HXT100G/fpga/coregen/coregen.cgp → example/HTG640/fpga/coregen/coregen.cgp
diff --git a/...fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco → ...fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco b/...fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco → ...fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco
diff --git a/...en_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco → ...en_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco b/...en_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco → ...en_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco
diff --git a/example/HXT100G/fpga/fpga.ucf → example/HTG640/fpga/fpga.ucf b/example/HXT100G/fpga/fpga.ucf → example/HTG640/fpga/fpga.ucf
diff --git a/example/HXT100G/fpga/fpga/Makefile → example/HTG640/fpga/fpga/Makefile b/example/HXT100G/fpga/fpga/Makefile → example/HTG640/fpga/fpga/Makefile
diff --git a/example/HXT100G/fpga/lib/eth → example/HTG640/fpga/lib/eth b/example/HXT100G/fpga/lib/eth → example/HTG640/fpga/lib/eth
diff --git a/example/HXT100G/fpga/rtl/debounce_switch.v → example/HTG640/fpga/rtl/debounce_switch.v b/example/HXT100G/fpga/rtl/debounce_switch.v → example/HTG640/fpga/rtl/debounce_switch.v
diff --git a/example/HXT100G/fpga/rtl/eth_gth_phy_quad.v → example/HTG640/fpga/rtl/eth_gth_phy_quad.v b/example/HXT100G/fpga/rtl/eth_gth_phy_quad.v → example/HTG640/fpga/rtl/eth_gth_phy_quad.v
diff --git a/example/HXT100G/fpga/rtl/fpga.v → example/HTG640/fpga/rtl/fpga.v b/example/HXT100G/fpga/rtl/fpga.v → example/HTG640/fpga/rtl/fpga.v
diff --git a/example/HXT100G/fpga/rtl/fpga_core.v → example/HTG640/fpga/rtl/fpga_core.v b/example/HXT100G/fpga/rtl/fpga_core.v → example/HTG640/fpga/rtl/fpga_core.v
diff --git a/example/HXT100G/fpga/rtl/gth_i2c_init.v → example/HTG640/fpga/rtl/gth_i2c_init.v b/example/HXT100G/fpga/rtl/gth_i2c_init.v → example/HTG640/fpga/rtl/gth_i2c_init.v
diff --git a/example/HXT100G/fpga/rtl/i2c_master.v → example/HTG640/fpga/rtl/i2c_master.v b/example/HXT100G/fpga/rtl/i2c_master.v → example/HTG640/fpga/rtl/i2c_master.v
diff --git a/example/HXT100G/fpga/rtl/sync_signal.v → example/HTG640/fpga/rtl/sync_signal.v b/example/HXT100G/fpga/rtl/sync_signal.v → example/HTG640/fpga/rtl/sync_signal.v
diff --git a/example/HXT100G/fpga/tb/fpga_core/Makefile → example/HTG640/fpga/tb/fpga_core/Makefile b/example/HXT100G/fpga/tb/fpga_core/Makefile → example/HTG640/fpga/tb/fpga_core/Makefile
diff --git a/...T100G/fpga/tb/fpga_core/test_fpga_core.py → ...TG640/fpga/tb/fpga_core/test_fpga_core.py b/...T100G/fpga/tb/fpga_core/test_fpga_core.py → ...TG640/fpga/tb/fpga_core/test_fpga_core.py
diff --git a/example/HXT100G/fpga_cxpt16/Makefile → example/HTG640/fpga_cxpt16/Makefile b/example/HXT100G/fpga_cxpt16/Makefile → example/HTG640/fpga_cxpt16/Makefile
diff --git a/example/HXT100G/fpga_cxpt16/README.md → example/HTG640/fpga_cxpt16/README.md b/example/HXT100G/fpga_cxpt16/README.md → example/HTG640/fpga_cxpt16/README.md
@@ -1,8 +1,8 @@
-# Verilog Ethernet HXT100G Crosspoint Switch Design
+# Verilog Ethernet HTG-640 Crosspoint Switch Design
 
 ## Introduction
 
-This design targets the HiTech Global HXT100G FPGA board.
+This design targets the HiTech Global HTG-640 (HTG-V6HXT-100GIG-565) FPGA board.
 
 The design forms a 16x16 crosspoint switch for 10G Ethernet.  It is capable of
 connecting any output port to any input port based on configuration frames

diff --git a/example/HXT100G/fpga_cxpt16/common/xilinx.mk → example/HTG640/fpga_cxpt16/common/xilinx.mk b/example/HXT100G/fpga_cxpt16/common/xilinx.mk → example/HTG640/fpga_cxpt16/common/xilinx.mk
diff --git a/example/HXT100G/fpga_cxpt16/coregen/Makefile → example/HTG640/fpga_cxpt16/coregen/Makefile b/example/HXT100G/fpga_cxpt16/coregen/Makefile → example/HTG640/fpga_cxpt16/coregen/Makefile
diff --git a/...e/HXT100G/fpga_cxpt16/coregen/coregen.cgp → ...le/HTG640/fpga_cxpt16/coregen/coregen.cgp b/...e/HXT100G/fpga_cxpt16/coregen/coregen.cgp → ...le/HTG640/fpga_cxpt16/coregen/coregen.cgp
diff --git a/...pt16/coregen/ten_gig_eth_pcs_pma_v2_6.xco → ...pt16/coregen/ten_gig_eth_pcs_pma_v2_6.xco b/...pt16/coregen/ten_gig_eth_pcs_pma_v2_6.xco → ...pt16/coregen/ten_gig_eth_pcs_pma_v2_6.xco
diff --git a/...en_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco → ...en_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco b/...en_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco → ...en_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco
diff --git a/example/HXT100G/fpga_cxpt16/fpga.ucf → example/HTG640/fpga_cxpt16/fpga.ucf b/example/HXT100G/fpga_cxpt16/fpga.ucf → example/HTG640/fpga_cxpt16/fpga.ucf
diff --git a/example/HXT100G/fpga_cxpt16/fpga/Makefile → example/HTG640/fpga_cxpt16/fpga/Makefile b/example/HXT100G/fpga_cxpt16/fpga/Makefile → example/HTG640/fpga_cxpt16/fpga/Makefile
diff --git a/example/HXT100G/fpga_cxpt16/lib/eth → example/HTG640/fpga_cxpt16/lib/eth b/example/HXT100G/fpga_cxpt16/lib/eth → example/HTG640/fpga_cxpt16/lib/eth
diff --git a/...HXT100G/fpga_cxpt16/rtl/debounce_switch.v → .../HTG640/fpga_cxpt16/rtl/debounce_switch.v b/...HXT100G/fpga_cxpt16/rtl/debounce_switch.v → .../HTG640/fpga_cxpt16/rtl/debounce_switch.v
diff --git a/...XT100G/fpga_cxpt16/rtl/eth_gth_phy_quad.v → ...HTG640/fpga_cxpt16/rtl/eth_gth_phy_quad.v b/...XT100G/fpga_cxpt16/rtl/eth_gth_phy_quad.v → ...HTG640/fpga_cxpt16/rtl/eth_gth_phy_quad.v
diff --git a/example/HXT100G/fpga_cxpt16/rtl/fpga.v → example/HTG640/fpga_cxpt16/rtl/fpga.v b/example/HXT100G/fpga_cxpt16/rtl/fpga.v → example/HTG640/fpga_cxpt16/rtl/fpga.v
diff --git a/example/HXT100G/fpga_cxpt16/rtl/fpga_core.v → example/HTG640/fpga_cxpt16/rtl/fpga_core.v b/example/HXT100G/fpga_cxpt16/rtl/fpga_core.v → example/HTG640/fpga_cxpt16/rtl/fpga_core.v
diff --git a/...le/HXT100G/fpga_cxpt16/rtl/gth_i2c_init.v → ...ple/HTG640/fpga_cxpt16/rtl/gth_i2c_init.v b/...le/HXT100G/fpga_cxpt16/rtl/gth_i2c_init.v → ...ple/HTG640/fpga_cxpt16/rtl/gth_i2c_init.v
diff --git a/example/HXT100G/fpga_cxpt16/rtl/i2c_master.v → example/HTG640/fpga_cxpt16/rtl/i2c_master.v b/example/HXT100G/fpga_cxpt16/rtl/i2c_master.v → example/HTG640/fpga_cxpt16/rtl/i2c_master.v
diff --git a/...ple/HXT100G/fpga_cxpt16/rtl/sync_signal.v → example/HTG640/fpga_cxpt16/rtl/sync_signal.v b/...ple/HXT100G/fpga_cxpt16/rtl/sync_signal.v → example/HTG640/fpga_cxpt16/rtl/sync_signal.v
diff --git a/...HXT100G/fpga_cxpt16/tb/fpga_core/Makefile → .../HTG640/fpga_cxpt16/tb/fpga_core/Makefile b/...HXT100G/fpga_cxpt16/tb/fpga_core/Makefile → .../HTG640/fpga_cxpt16/tb/fpga_core/Makefile
diff --git a/...pga_cxpt16/tb/fpga_core/test_fpga_core.py → ...pga_cxpt16/tb/fpga_core/test_fpga_core.py b/...pga_cxpt16/tb/fpga_core/test_fpga_core.py → ...pga_cxpt16/tb/fpga_core/test_fpga_core.py