ARP: resolve IP multicast

example/VCU1525/fpga_10g/Makefile

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+# Targets
+TARGETS:=
+
+# Subdirectories
+SUBDIRS = fpga
+SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
+
+# Rules
+.PHONY: all
+all: $(SUBDIRS) $(TARGETS)
+
+.PHONY: $(SUBDIRS)
+$(SUBDIRS):
+	cd $@ && $(MAKE)
+
+.PHONY: $(SUBDIRS_CLEAN)
+$(SUBDIRS_CLEAN):
+	cd $(@:.clean=) && $(MAKE) clean
+
+.PHONY: clean
+clean: $(SUBDIRS_CLEAN)
+	-rm -rf $(TARGETS)
+
+program:
+	#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit

example/VCU1525/fpga_10g/README.md

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+# Verilog Ethernet VCU1525 Example Design
+
+## Introduction
+
+This example design targets the Xilinx VCU1525 FPGA board.
+
+The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
+will echo back any packets received.  The design will also respond correctly
+to ARP requests.  The design also enables the gigabit Ethernet interface for
+testing with a QSFP loopback adapter.  
+
+FPGA: xcvu9p-fsgd2104-2L-e
+PHY: 10G BASE-R PHY IP core and internal GTY transceiver
+
+## How to build
+
+Run make to build.  Ensure that the Xilinx Vivado toolchain components are
+in PATH.  
+
+## How to test
+
+Run make program to program the VCU1525 board with Vivado.  Then run
+netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234.  Any text
+entered into netcat will be echoed back after pressing enter.  
+
+

example/VCU1525/fpga_10g/common/vivado.mk

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+###################################################################
+# 
+# Xilinx Vivado FPGA Makefile
+# 
+# Copyright (c) 2016 Alex Forencich
+# 
+###################################################################
+# 
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - space-separated list of source files
+# INC_FILES - space-separated list of include files
+# XDC_FILES - space-separated list of timing constraint files
+# XCI_FILES - space-separated list of IP XCI files
+# 
+# Example:
+# 
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+# 
+###################################################################
+
+# phony targets
+.PHONY: clean fpga
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include ../$(CONFIG)
+
+SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
+INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
+XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES))
+
+ifdef XDC_FILES
+  XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES))
+else
+  XDC_FILES_REL = $(FPGA_TOP).xdc
+endif
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and project files
+###################################################################
+
+all: fpga
+
+fpga: $(FPGA_TOP).bit
+
+tmpclean:
+	-rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean: tmpclean
+	-rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+
+distclean: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+%.xpr: Makefile $(XCI_FILES_REL)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl
+	echo "add_files -fileset sources_1 defines.v" >> create_project.tcl
+	for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done
+	for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done
+	for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done
+	echo "exit" >> create_project.tcl
+	vivado -nojournal -nolog -mode batch -source create_project.tcl
+
+# synthesis run
+%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
+	echo "open_project $*.xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	echo "exit" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
+	echo "open_project $*.xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "exit" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# bit file
+%.bit: %.runs/impl_1/%_routed.dcp
+	echo "open_project $*.xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force $*.bit" >> generate_bit.tcl
+	echo "exit" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp $@ rev/$*_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_rev$$COUNT.$$EXT";