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[transform] e2e UT for packed gemm (#892)
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10 changes: 10 additions & 0 deletions
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tao_compiler/mlir/disc/tests/disc-transform/data/packed_matmul_nn_p_512x1024_f32.mlir
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module attributes {tf.versions = {bad_consumers = [], min_consumer = 0 : i32, producer = 0 : i32}} { | ||
func.func @main(%arg0: tensor<?x?xf32>) -> (tensor<?x?xf32>) attributes {tf.entry_function = {inputs = "{{INPUTS}}", outputs = "{{OUTPUTS}}", input_placements="{{INPUT_PLACEMENTS}}", output_placements="{{OUTPUT_PLACEMENTS}}"}} { | ||
%graph = tf_executor.graph { | ||
%0:2 = tf_executor.island wraps "tf.Const"() {value = dense<-0.8> : tensor<512x1024xf32>} : () -> tensor<512x1024xf32> | ||
%1:2 = tf_executor.island wraps "tf.MatMul"(%arg0, %0) {transpose_a = false, transpose_b = false} : (tensor<?x?xf32>, tensor<512x1024xf32>) -> (tensor<?x?xf32>) | ||
tf_executor.fetch %1 : tensor<?x?xf32> | ||
} | ||
return %graph : tensor<?x?xf32> | ||
} | ||
} |
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tao_compiler/mlir/disc/tests/disc-transform/data/packed_matmul_nn_p_f32_large_schedule.mlir
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transform.structured.canonicalized_sequence failures(propagate) { | ||
^bb1(%arg1: !pdl.operation): | ||
%fill = transform.structured.match ops{["linalg.fill"]} in %arg1 | ||
%matmul = transform.structured.match ops{["linalg.matmul"]} in %arg1 | ||
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%0:2 = transform.structured.tile_to_foreach_thread_op %matmul num_threads [1, 1] | ||
transform.structured.fuse_into_containing_op %fill into %0#0 | ||
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// first level tile and fuse matmul and fill op. | ||
%1:3 = transform.structured.fuse %0#1 {tile_sizes = [288, 48, 0], tile_interchange = [0, 1, 2]} | ||
// second level tile and fuse matmul and fill op. | ||
%2:3 = transform.structured.fuse %1#0 {tile_sizes = [6, 16, 0], tile_interchange = [0, 1, 2]} | ||
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// gemm reduction axis tiling | ||
%3:2 = transform.structured.tile %2#0 [0, 0, 1] {interchange=[0, 1, 2]} | ||
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// clean up | ||
%func0 = transform.structured.match ops{["func.func"]} in %arg1 | ||
transform.disc.apply_patterns %func0 {canonicalization} | ||
// fold two extract_slice ops generated by two-level tiling. It's needed to enable following | ||
// pad and hosit schedule. | ||
%weight_inner_slice = get_producer_of_operand %3#0[1] : (!pdl.operation) -> !pdl.operation | ||
transform.disc.fold_producer_extract_slice %weight_inner_slice {max_repeat_num = 2} | ||
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// pad to match the requirement of hardware vector/tensor instruction. | ||
%4 = transform.structured.pad %3#0 {padding_values=[0.0 : f32, 0.0 : f32, 0.0 : f32], padding_dimensions=[0, 1, 2], pack_paddings=[1, 1, 0], hoist_paddings=[0, 0, 0], transpose_paddings=[[1, 0], [0, 1], [0, 1]]} | ||
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%pad_for_input = get_producer_of_operand %4[0] : (!pdl.operation) -> !pdl.operation | ||
%pad_for_weight = get_producer_of_operand %4[1] : (!pdl.operation) -> !pdl.operation | ||
%foreach_op = transform.structured.match ops{["scf.foreach_thread"]} in %arg1 | ||
%loop_for_outter_most_n = transform.loop.get_parent_for %4 { num_loops = 4} : (!pdl.operation) -> !pdl.operation | ||
transform.disc.cache_read {padded} %pad_for_input at %loop_for_outter_most_n with tile_levels = [1, 1] tile_sizes = [6, 1] permutation = [0, 2, 3, 1] | ||
transform.disc.cache_read {padded} %pad_for_weight at %foreach_op with tile_levels = [1, 1] tile_sizes = [1, 16] permutation = [2, 0, 1, 3] | ||
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%func1 = transform.structured.match ops{["func.func"]} in %arg1 | ||
transform.disc.apply_patterns %func1 {canonicalization} | ||
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%pack_op = transform.structured.match ops{["disc_linalg_ext.multi_level_pack"]} in %arg1 | ||
transform.disc.lower_multi_level_pack_to_loop %pack_op | ||
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%func2 = transform.structured.match ops{["func.func"]} in %arg1 | ||
transform.disc.apply_patterns %func2 {canonicalization} | ||
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%func3 = transform.structured.match ops{["func.func"]} in %arg1 | ||
transform.structured.vectorize %func3 {vectorize_padding} | ||
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%func4 = transform.structured.match ops{["func.func"]} in %arg1 | ||
transform.disc.apply_patterns %func4 {canonicalization} | ||
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transform.disc.bufferize %arg1 | ||
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transform.lower_vectors { | ||
contraction_lowering = "outerproduct", | ||
multireduction_lowering = "innerparallel", | ||
split_transfers = "linalg-copy", | ||
// stages = [0, 1, 2, 3, 4, 5, 6, 7], | ||
stages = [0, 1, 2, 3], | ||
transpose_avx2_lowering = false, | ||
transpose_lowering = "eltwise", | ||
unroll_vector_transfers = true | ||
} | ||
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transform.lower_vectors { | ||
contraction_lowering = "outerproduct", | ||
multireduction_lowering = "innerparallel", | ||
split_transfers = "linalg-copy", | ||
// stages = [0, 1, 2, 3, 4, 5, 6, 7], | ||
stages = [5, 6, 7], | ||
transpose_avx2_lowering = false, | ||
transpose_lowering = "eltwise", | ||
unroll_vector_transfers = true | ||
} | ||
} |
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tao_compiler/mlir/disc/tests/disc-transform/packed_matmul.cc
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/* Copyright 2022 The BladeDISC Authors. All Rights Reserved. | ||
Licensed under the Apache License, Version 2.0 (the "License"); | ||
you may not use this file except in compliance with the License. | ||
You may obtain a copy of the License at | ||
http://www.apache.org/licenses/LICENSE-2.0 | ||
Unless required by applicable law or agreed to in writing, software | ||
distributed under the License is distributed on an "AS IS" BASIS, | ||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
See the License for the specific language governing permissions and | ||
limitations under the License. | ||
==============================================================================*/ | ||
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#include "tensorflow/compiler/mlir/disc/tests/mlir_feature_test.h" | ||
#include "tensorflow/compiler/mlir/disc/tests/mlir_test.h" | ||
#include "tensorflow/core/platform/test.h" | ||
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namespace mlir_test { | ||
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const std::string c_ft_path = | ||
"tensorflow/compiler/mlir/disc/tests/disc-transform/data/"; | ||
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static bool init_threads = []() { | ||
setenv("OMP_NUM_THREADS", "1", 1); | ||
return true; | ||
}(); | ||
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TEST(PackedMatmul, F32_304x1024x512) { | ||
EnvSetting setting = { | ||
{"DISC_TRANSFORM_SCHEDULE_FILE", | ||
{c_ft_path + "packed_matmul_nn_p_f32_large_schedule.mlir", false}}, | ||
{"DISC_ENABLE_TRANSFORM_SCHEDULE", {"1", false}}, | ||
{"DISC_ENABLE_SHAPE_CONSTRAINT_IR", {"1", false}}, | ||
{"DISC_MEM_INTENSIVE_OPT_EXPERIMENTAL", {"0", false}}}; | ||
EnvSettingContext ctx(setting); | ||
EXPECT_TRUE(feature_test_main( | ||
/*mlir_file_path*/ c_ft_path + "packed_matmul_nn_p_512x1024_f32.mlir", | ||
/*backend_types*/ {BackendType::kAArch64}, | ||
/*num_inputs*/ 1, | ||
/*num_outputs*/ 1, | ||
/*input_descriptors*/ {"304x512xf32_X"}, | ||
/*output_descriptors*/ {"f32_X"}, | ||
/*input_vals*/ {}, | ||
/*expected_output_vals*/ {}, | ||
/*profiling*/ true)); | ||
} | ||
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} // namespace mlir_test |
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