Merge remote-tracking branch 'xilinx/master' into tools_upgrade

Pull changes from Xilinx master into ADI master. This is in preparation to do the upgrade to Vivado 2018.1. Signed-off-by: Alexandru Ardelean <[email protected]>
analogdevicesinc · Aug 6, 2018 · dd100de · dd100de
2 parents 0942b0f + 45f9852
commit dd100de
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diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,mixer.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,mixer.txt
@@ -16,6 +16,7 @@ Required properties:
  - xlnx,dma-addr-width: dma address width, valid values are 32 and 64
  - xlnx,bpc: bits per component for mixer
  - xlnx,ppc: pixel per clock for mixer
+ - xlnx,num-layers: Total number of layers (excluding logo)
  - layer_[x]: node for [x] layer
  - xlnx,layer-id: layer identifier number
  - xlnx,vformat: video format for layer. See list of supported formats below.
@@ -24,6 +25,8 @@ Required properties:
    not required for overlay layers
  - xlnx,layer-max-height: max layer height, mandatory for master layer
    Not required for overlay layers
+ - xlnx,layer-primary: denotes the primary layer, should be mentioned in node
+   of layer which is expected to be constructing the primary plane
 
 Optional properties:
  - dmas: dma attach to layer, mandatory for master layer
@@ -37,6 +40,8 @@ Optional properties:
  - xlnx,layer-scale: denotes layer can be scale to 2x and 4x
  - xlnx,logo-layer: denotes logo layer is enable
  - logo: logo layer
+ - xlnx,bridge: phandle to bridge node.
+   This handle is required only when VTC is connected as bridge.
 
 Supported Formats:
 	Mixer IP Format		Driver supported Format String
@@ -76,6 +81,7 @@ Example:
 		xlnx,ppc = <2>;
 		xlnx,num-layers = <8>;
 		xlnx,logo-layer;
+		xlnx,bridge = <&v_tc_0>;
 
 		mixer_port: mixer_port@0 {
 			reg = <0>;
@@ -91,6 +97,7 @@ Example:
 			dmas = <&axi_vdma_0 0>;
 			dma-names = "dma0";
 			xlnx,layer-streaming;
+			xlnx,layer-primary;
 		};
 		xv_mix_overlay_1: layer_1 {
 			xlnx,layer-id = <1>;

diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,pl-disp.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,pl-disp.txt
@@ -20,13 +20,18 @@ Required properties:
   Documentation/devicetree/bindings/graph.txt.
 - reg: Base address and size of device
 
+Optional properties:
+ - xlnx,bridge: bridge phandle
+   This handle is required only when VTC is connected as bridge.
+
 Example:
 
 	drm-pl-disp-drv {
 		compatible = "xlnx,pl-disp";
 		dmas = <&axi_vdma_0 0>;
 		dma-names = "dma0";
 		xlnx,vformat = "YUYV";
+		xlnx,bridge = <&v_tc_0>;
 		pl_disp_port@0 {
 			reg = <0>;
 			endpoint {

diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,vtc.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,vtc.txt
@@ -0,0 +1,27 @@
+Device-Tree bindings for Xilinx Video Timing Controller(VTC)
+
+Xilinx VTC is a general purpose video timing generator and detector.
+The input side of this core automatically detects horizontal and
+vertical synchronization, pulses, polarity, blanking timing and active pixels.
+While on the output, it generates the horizontal and vertical blanking and
+synchronization pulses used with a standard video system including support
+for programmable pulse polarity.
+
+The core is commonly used with Video in to AXI4-Stream core to detect the
+format and timing of incoming video data or with AXI4-Stream to Video out core
+to generate outgoing video timing for downstream sinks like a video monitor.
+
+For details please refer to
+https://www.xilinx.com/support/documentation/ip_documentation/v_tc/v6_1/pg016_v_tc.pdf
+
+Required properties:
+ - compatible: value should be "xlnx,bridge-v-tc-6.1"
+ - reg: base address and size of the VTC IP
+ - xlnx,pixels-per-clock: Pixels per clock of the stream. Can be 1, 2 or 4.
+
+Example:
+	v_tc_0: v_tc@80030000 {
+			compatible = "xlnx,bridge-v-tc-6.1";
+			reg = <0x0 0x80030000 0x0 0x10000>;
+			xlnx,pixels-per-clock = <2>;
+	};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt b/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
@@ -31,6 +31,7 @@ Optional properties:
 - xlnx,dout-default-2 : as above but the second channel
 - xlnx,gpio2-width : as above but for the second channel
 - xlnx,tri-default-2 : as above but for the second channel
+- xlnx,no-init : No initialisation at probe
 
 
 Example:

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -267,6 +267,10 @@
 	clocks = <&clk 75>;
 };
 
+&lpd_watchdog {
+	clocks = <&clk 75>;
+};
+
 &xilinx_ams {
 	clocks = <&clk 70>;
 };

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
@@ -225,6 +225,10 @@
 	clocks = <&clk250>;
 };
 
+&lpd_watchdog {
+	clocks = <&clk250>;
+};
+
 &zynqmp_dpsub {
 	clocks = <&dp_aclk>, <&dp_aud_clk>, <&drm_clock>;
 };

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
@@ -486,7 +486,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_spi0_default>;
 
-	spi0_flash0: flash0@0 {
+	spi0_flash0: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "sst,sst25wf080", "jedec,spi-nor";
@@ -506,7 +506,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_spi1_default>;
 
-	spi1_flash0: flash0@0 {
+	spi1_flash0: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
@@ -107,6 +107,7 @@
 
 	ltc2954: ltc2954 { /* U7 */
 		compatible = "lltc,ltc2954", "lltc,ltc2952";
+		status = "disabled";
 		trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */
 		/* If there is HW watchdog on mezzanine this signal should be connected there */
 		watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */
@@ -473,7 +474,6 @@
 &sdhci0 {
 	status = "okay";
 	no-1-8-v;
-	broken-cd; /* CD has to be enabled by default */
 	disable-wp;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_sdhci0_default>;

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -442,6 +442,7 @@
 				temperature-stability = <50>;
 				factory-fout = <300000000>;
 				clock-frequency = <300000000>;
+				clock-output-names = "si570_user";
 			};
 		};
 		i2c@3 {
@@ -455,6 +456,7 @@
 				temperature-stability = <50>; /* copy from zc702 */
 				factory-fout = <156250000>;
 				clock-frequency = <148500000>;
+				clock-output-names = "si570_mgt";
 			};
 		};
 		i2c@4 {

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
@@ -141,9 +141,9 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <4>;
-			tca6416_u97: gpio@21 {
+			tca6416_u97: gpio@20 {
 				compatible = "ti,tca6416";
-				reg = <0x21>;
+				reg = <0x20>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				/*

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
@@ -85,9 +85,9 @@
 	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 
-	tca6416_u97: gpio@21 {
+	tca6416_u97: gpio@20 {
 		compatible = "ti,tca6416";
-		reg = <0x21>;
+		reg = <0x20>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		/*
@@ -156,10 +156,15 @@
 			};
 		};
 
-		i2c@4 {
+		i2c@3 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <4>;
+			reg = <3>;
+			ina226@40 { /* u183 */
+				compatible = "ti,ina226";
+				reg = <0x40>;
+				shunt-resistor = <5000>;
+			};
 		};
 
 		i2c@5 {
@@ -174,7 +179,7 @@
 			reg = <7>;
 		};
 
-		/* 3, 6 not connected */
+		/* 4, 6 not connected */
 	};
 };
 

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -415,6 +415,7 @@
 				temperature-stability = <50>;
 				factory-fout = <300000000>;
 				clock-frequency = <300000000>;
+				clock-output-names = "si570_user";
 			};
 		};
 		i2c@3 {
@@ -428,6 +429,7 @@
 				temperature-stability = <50>; /* copy from zc702 */
 				factory-fout = <156250000>;
 				clock-frequency = <148500000>;
+				clock-output-names = "si570_mgt";
 			};
 		};
 		i2c@4 {

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
@@ -336,6 +336,7 @@
 				temperature-stability = <50>;
 				factory-fout = <300000000>;
 				clock-frequency = <300000000>;
+				clock-output-names = "si570_user";
 			};
 		};
 		i2c@3 {
@@ -349,6 +350,7 @@
 				temperature-stability = <50>;
 				factory-fout = <156250000>;
 				clock-frequency = <148500000>;
+				clock-output-names = "si570_mgt";
 			};
 		};
 		i2c@4 {

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -878,8 +878,8 @@
 			interrupts = <0 133 4>;
 			power-domains = <&pd_sata>;
 			#stream-id-cells = <4>;
-			iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
-				 <&smmu 0x4c2>, <&smmu 0x4c3>;
+			/* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, */
+			/*	 <&smmu 0x4c2>, <&smmu 0x4c3>; */
 			/* dma-coherent; */
 		};
 
@@ -919,7 +919,7 @@
 			compatible = "arm,mmu-500";
 			reg = <0x0 0xfd800000 0x0 0x20000>;
 			#iommu-cells = <1>;
-			status = "disabled";
+			status = "okay";
 			#global-interrupts = <1>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 155 4>,
@@ -1083,6 +1083,15 @@
 			timeout-sec = <10>;
 		};
 
+		lpd_watchdog: watchdog@ff150000 {
+			compatible = "cdns,wdt-r1p2";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 52 1>;
+			reg = <0x0 0xff150000 0x0 0x1000>;
+			timeout-sec = <10>;
+		};
+
 		xilinx_ams: ams@ffa50000 {
 			compatible = "xlnx,zynqmp-ams";
 			status = "disabled";

diff --git a/arch/arm64/configs/xilinx_zynqmp_defconfig b/arch/arm64/configs/xilinx_zynqmp_defconfig
@@ -140,9 +140,12 @@ CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ARASAN=y
 CONFIG_MTD_SPI_NOR=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_CONFIGFS=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_XILINX_SDFEC=y
 CONFIG_XILINX_JESD204B=y
 CONFIG_XILINX_JESD204B_PHY=y
 CONFIG_EEPROM_AT24=y
@@ -177,6 +180,7 @@ CONFIG_REALTEK_PHY=y
 CONFIG_SMSC_PHY=y
 CONFIG_STE10XP=y
 CONFIG_VITESSE_PHY=y
+CONFIG_XILINX_GMII2RGMII=y
 CONFIG_USB_USBNET=y
 CONFIG_WL18XX=y
 CONFIG_WLCORE_SPI=y

diff --git a/drivers/clk/idt/clk-idt8t49n24x-core.c b/drivers/clk/idt/clk-idt8t49n24x-core.c
@@ -46,8 +46,10 @@
 #define IDT24x_VCO_MAX			4000004000u
 #define IDT24x_VCO_OPT			3500000000u
 #define IDT24x_MIN_INT_DIVIDER		6
+#define IDT24x_MIN_NS1			4
+#define IDT24x_MAX_NS1			6
 
-u8 q0_ns1_options[3] = { 4, 5, 6 };
+static u8 q0_ns1_options[3] = { 5, 6, 4 };
 
 /**
  * bits_to_shift - num bits to shift given specified mask
@@ -295,11 +297,8 @@ static int idt24x_calc_div_q0(struct clk_idt24x_chip *chip)
 		"%s. requested: %u, min_div: %u, max_div: %u",
 		__func__, chip->clk[0].requested, min_div, max_div);
 
-	min_ns2 = div64_u64(
-		(u64)min_div,
-		q0_ns1_options[ARRAY_SIZE(q0_ns1_options) - 1] * 2);
-	max_ns2 = div64_u64(
-		(u64)max_div, q0_ns1_options[0] * 2);
+	min_ns2 = div64_u64((u64)min_div, IDT24x_MAX_NS1 * 2);
+	max_ns2 = div64_u64((u64)max_div, IDT24x_MIN_NS1 * 2);
 
 	dev_dbg(&chip->i2c_client->dev,
 		"%s. min_ns2: %u, max_ns2: %u", __func__, min_ns2, max_ns2);
@@ -343,7 +342,7 @@ static int idt24x_calc_div_q0(struct clk_idt24x_chip *chip)
 					   current_vco > best_vco)
 					use = true;
 				if (use) {
-					chip->divs.ns1_q0 = q0_ns1_options[x];
+					chip->divs.ns1_q0 = x;
 					chip->divs.ns2_q0 = y;
 					best_vco = current_vco;
 				}
@@ -353,10 +352,9 @@ static int idt24x_calc_div_q0(struct clk_idt24x_chip *chip)
 	}
 
 	dev_dbg(&chip->i2c_client->dev,
-		"%s. best: (ns1=%u * ns2=%u * 2 * %u) == %u",
-		__func__, chip->divs.ns1_q0, chip->divs.ns2_q0,
-		chip->clk[0].requested,
-		best_vco);
+		"%s. best: (ns1=%u [/%u] * ns2=%u * 2 * %u) == %u",
+		__func__, chip->divs.ns1_q0, q0_ns1_options[chip->divs.ns1_q0],
+		chip->divs.ns2_q0, chip->clk[0].requested, best_vco);
 	return 0;
 }
 
@@ -380,16 +378,17 @@ static int idt24x_calc_divs(struct clk_idt24x_chip *chip)
 		return result;
 
 	dev_dbg(&chip->i2c_client->dev,
-		"%s: after idt24x_calc_div_q0. ns1: %u, ns2: %u",
-		__func__, chip->divs.ns1_q0, chip->divs.ns2_q0);
+		"%s: after idt24x_calc_div_q0. ns1: %u [/%u], ns2: %u",
+		__func__, chip->divs.ns1_q0, q0_ns1_options[chip->divs.ns1_q0],
+		chip->divs.ns2_q0);
 
 	chip->divs.dsmint = 0;
 	chip->divs.dsmfrac = 0;
 
-	if (chip->divs.ns1_q0 > 0) {
+	if (chip->clk[0].requested > 0) {
 		/* Q0 is in use and is governing the actual VCO freq */
-		vco = chip->divs.ns1_q0 * chip->divs.ns2_q0 * 2 *
-			chip->clk[0].requested;
+		vco = q0_ns1_options[chip->divs.ns1_q0] * chip->divs.ns2_q0 *
+			2 * chip->clk[0].requested;
 	} else {
 		u32 freq = 0;
 		u32 walk;
@@ -690,10 +689,10 @@ static int idt24x_update_device(struct clk_idt24x_chip *chip)
 
 	dev_dbg(&client->dev,
 		"%s: setting IDT24x_REG_NS1_Q0 (val %u @ 0x%x)",
-		__func__, chip->divs.ns1_q0 >> 8, IDT24x_REG_NS1_Q0);
+		__func__, chip->divs.ns1_q0, IDT24x_REG_NS1_Q0);
 	err = i2cwritewithmask(
 		client, chip->regmap, IDT24x_REG_NS1_Q0,
-		(chip->divs.ns1_q0 >> 8) & IDT24x_REG_NS1_Q0_MASK,
+		chip->divs.ns1_q0 & IDT24x_REG_NS1_Q0_MASK,
 		chip->reg_ns1_q0, IDT24x_REG_NS1_Q0_MASK);
 	if (err) {
 		dev_err(&client->dev,