util_axis_fifo_asym: Updated parameters according to HDL changes

Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
analogdevicesinc · Apr 22, 2024 · d5a925d · d5a925d
1 parent 02327bf
commit d5a925d
Showing 1 changed file with 5 additions and 4 deletions.
diff --git a/util_axis_fifo_asym/system_bd.tcl b/util_axis_fifo_asym/system_bd.tcl
@@ -53,14 +53,15 @@ create_bd_port -dir I output_clk
 ad_ip_instance util_axis_fifo_asym util_axis_fifo_asym_DUT [list \
   ASYNC_CLK 1 \
   S_DATA_WIDTH $INPUT_WIDTH \
-  S_ADDRESS_WIDTH 5 \
+  ADDRESS_WIDTH 5 \
   M_DATA_WIDTH $OUTPUT_WIDTH \
   M_AXIS_REGISTERED 1 \
-  ALMOST_EMPTY_THRESHOLD 4 \
-  ALMOST_FULL_THRESHOLD 4 \
+  ALMOST_EMPTY_THRESHOLD 16 \
+  ALMOST_FULL_THRESHOLD 16 \
   TLAST_EN 1 \
   TKEEP_EN 1 \
-  S_FIFO_LIMITED 0 \
+  FIFO_LIMITED 1 \
+  ADDRESS_WIDTH_PERSPECTIVE 0 \
 ]
 
 ad_connect input_clk util_axis_fifo_asym_DUT/s_axis_aclk