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util_axis_fifo_asym: Initial testbench commit
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Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
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IstvanZsSzekely committed Oct 18, 2024
1 parent e32d8e8 commit d5f1a56
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59 changes: 59 additions & 0 deletions testbenches/ip/util_axis_fifo_asym/Makefile
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####################################################################################
####################################################################################
## Copyright 2022(c) Analog Devices, Inc.
####################################################################################
####################################################################################

# All test-bench dependencies except test programs
SV_DEPS += ../../../library/utilities/utils.svh
SV_DEPS += ../../../library/utilities/logger_pkg.sv
SV_DEPS += ../../../library/regmaps/reg_accessor.sv
SV_DEPS += ../../../library/vip/amd/m_axis_sequencer.sv
SV_DEPS += ../../../library/vip/amd/s_axis_sequencer.sv
SV_DEPS += ../../../library/vip/amd/m_axi_sequencer.sv
SV_DEPS += ../../../library/vip/amd/s_axi_sequencer.sv
SV_DEPS += ../../../library/utilities/test_harness_env.sv
SV_DEPS += ../../../library/regmaps/adi_peripheral_pkg.sv
SV_DEPS += ../../../library/regmaps/adi_regmap_pkg.sv
SV_DEPS += ../../../library/drivers/common/mailbox.sv
SV_DEPS += ../../../library/drivers/common/x_monitor.sv
SV_DEPS += ../../../library/drivers/common/scoreboard.sv
SV_DEPS += ../../../library/drivers/common/filter.sv
SV_DEPS += ../../../library/drivers/common/interfaces.svh
SV_DEPS += ../../../library/drivers/common/watchdog.sv
SV_DEPS += environment.sv
SV_DEPS += system_tb.sv

ENV_DEPS += system_project.tcl
ENV_DEPS += system_bd.tcl
ENV_DEPS += ../../../scripts/adi_sim.tcl
ENV_DEPS += ../../../scripts/run_sim.tcl

LIB_DEPS := util_cdc
LIB_DEPS += util_axis_fifo
LIB_DEPS += util_axis_fifo_asym

# default test program
TP := test_program

# config files should have the following format
# cfg_<param1>_<param2>.tcl
CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
#$(warning $(CFG_FILES))

# List of tests and configuration combinations that has to be run
# Format is: <configuration>:<test name>
TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP))

include ../../../scripts/project-sim.mk

# usage :
#
# run specific test on a specific configuration in gui mode
# make CFG=cfg2_fsync TST=test_frame_delay MODE=gui
#
# run all test from a configuration
# make cfg1_mm2mm_default

####################################################################################
####################################################################################
27 changes: 27 additions & 0 deletions testbenches/ip/util_axis_fifo_asym/README.md
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Usage :

Run all tests in batch mode:

make


Run all tests in GUI mode:

make MODE=gui


Run specific test on a specific configuration in gui mode:

make CFG=<name of cfg> TST=<name of test> MODE=gui


Run all test from a configuration:

make <name of cfg>


Where:

* <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
* <name of test> is a file from the tests directory without the tcl extension

28 changes: 28 additions & 0 deletions testbenches/ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl
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global ad_project_params

set random_width [expr int(8*pow(2, int(7.0*rand()+1)))]
set INPUT_WIDTH $random_width
set ad_project_params(INPUT_WIDTH) $INPUT_WIDTH

set random_width [expr int(8*pow(2, int(7.0*rand()+1)))]
set OUTPUT_WIDTH $random_width
set ad_project_params(OUTPUT_WIDTH) $OUTPUT_WIDTH

set FIFO_LIMITED [expr int(rand()*2)]
set ad_project_params(FIFO_LIMITED) $FIFO_LIMITED

if {$FIFO_LIMITED} {
if {$INPUT_WIDTH > $OUTPUT_WIDTH} {
set RATIO $INPUT_WIDTH/$OUTPUT_WIDTH
} else {
set RATIO $OUTPUT_WIDTH/$INPUT_WIDTH
}
} else {
set RATIO 1
}

set random_width [expr int(int(log($RATIO)/log(2))+4.0*rand()+1)]
set ad_project_params(ADDRESS_WIDTH) $random_width

set ad_project_params(INPUT_CLK) [expr int(rand()*9000)+1000]
set ad_project_params(OUTPUT_CLK) [expr int(rand()*9000)+1000]
188 changes: 188 additions & 0 deletions testbenches/ip/util_axis_fifo_asym/environment.sv
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`include "utils.svh"

package environment_pkg;

import m_axi_sequencer_pkg::*;
import s_axi_sequencer_pkg::*;
import m_axis_sequencer_pkg::*;
import s_axis_sequencer_pkg::*;
import logger_pkg::*;

import axi_vip_pkg::*;
import axi4stream_vip_pkg::*;
import test_harness_env_pkg::*;
import scoreboard_pkg::*;
import x_monitor_pkg::*;

import `PKGIFY(test_harness, mng_axi_vip)::*;
import `PKGIFY(test_harness, ddr_axi_vip)::*;

import `PKGIFY(test_harness, input_axis)::*;
import `PKGIFY(test_harness, output_axis)::*;

class environment extends test_harness_env;

virtual interface clk_if input_clk_if;
virtual interface clk_if output_clk_if;

// agents and sequencers
`AGENT(test_harness, input_axis, mst_t) input_axis_agent;
`AGENT(test_harness, output_axis, slv_t) output_axis_agent;

m_axis_sequencer #(`AGENT(test_harness, input_axis, mst_t),
`AXIS_VIP_PARAMS(test_harness, input_axis)
) input_axis_seq;
s_axis_sequencer #(`AGENT(test_harness, output_axis, slv_t)) output_axis_seq;

x_axis_monitor #(`AGENT(test_harness, input_axis, mst_t)) input_axis_mon;
x_axis_monitor #(`AGENT(test_harness, output_axis, slv_t)) output_axis_mon;

scoreboard scoreboard_inst;

//============================================================================
// Constructor
//============================================================================
function new (
virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if,
virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if,
virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if,

virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if,

virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if,
virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if,

virtual interface clk_if input_clk_if,
virtual interface clk_if output_clk_if,

virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, input_axis)) input_axis_vip_if,
virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, output_axis)) output_axis_vip_if
);

// creating the agents
super.new(sys_clk_vip_if,
dma_clk_vip_if,
ddr_clk_vip_if,
sys_rst_vip_if,
mng_vip_if,
ddr_vip_if);

this.input_clk_if = input_clk_if;
this.output_clk_if = output_clk_if;

input_axis_agent = new("Input AXI Stream Agent", input_axis_vip_if);
output_axis_agent = new("Output AXI Stream Agent", output_axis_vip_if);

input_axis_seq = new(input_axis_agent);
output_axis_seq = new(output_axis_agent);

input_axis_mon = new("Input AXIS Transaction Monitor", input_axis_agent);
output_axis_mon = new("Output AXIS Transaction Monitor", output_axis_agent);

scoreboard_inst = new("Verification Environment Scoreboard");

endfunction

//============================================================================
// Configure environment
//============================================================================
task configure();

// configuration for input
this.input_axis_seq.set_stop_policy(STOP_POLICY_PACKET);
this.input_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR);
this.input_axis_seq.set_descriptor_gen_mode(1);
this.input_axis_seq.set_data_beat_delay(0);
this.input_axis_seq.set_descriptor_delay(0);
this.input_axis_seq.set_inactive_drive_output_0();

// configuration for output
this.output_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE);

// this.output_axis_seq.set_use_variable_ranges();
// this.output_axis_seq.set_high_time_range(1,1);
// this.output_axis_seq.set_low_time_range(0,0);

// this.output_axis_seq.clr_use_variable_ranges();
// this.output_axis_seq.set_high_time(1);
// this.output_axis_seq.set_low_time(1);

endtask

//============================================================================
// Start environment
// - Connect all the agents to the scoreboard
// - Start the agents
//============================================================================
task start();

super.start();

input_clk_if.start_clock(`INPUT_CLK);
output_clk_if.start_clock(`OUTPUT_CLK);

input_axis_agent.start_master();
output_axis_agent.start_slave();

scoreboard_inst.set_source_stream(input_axis_mon);
scoreboard_inst.set_sink_stream(output_axis_mon);

endtask

//============================================================================
// Start the test
// - start the RX scoreboard and sequencer
// - start the TX scoreboard and sequencer
// - setup the RX DMA
// - setup the TX DMA
//============================================================================
task test();

fork
input_axis_seq.run();
output_axis_seq.run();

input_axis_mon.run();
output_axis_mon.run();

scoreboard_inst.run();
join_none

endtask


//============================================================================
// Post test subroutine
//============================================================================
task post_test();
// Evaluate the scoreboard's results
endtask

//============================================================================
// Run subroutine
//============================================================================
task run;

//pre_test();
test();

endtask

//============================================================================
// Stop subroutine
//============================================================================
task stop;

super.stop();

input_axis_seq.stop();
input_axis_agent.stop_master();
output_axis_agent.stop_slave();

post_test();

endtask

endclass

endpackage
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