fix (#3797)

Co-authored-by: ring630 <@gmail.com>
ansys · Oct 25, 2023 · 5507831 · 5507831
1 parent 8af5e38
commit 5507831
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diff --git a/_unittest/test_00_EDB.py b/_unittest/test_00_EDB.py
@@ -1387,6 +1387,8 @@ def test_107_create_edge_ports(self):
         gap_port.name = "gap_port"
         assert gap_port.name == "gap_port"
         assert isinstance(gap_port.renormalize_z0, tuple)
+        gap_port.is_circuit_port = True
+        assert gap_port.is_circuit_port
         edb.close()
 
     def test_108_create_dc_simulation(self):

diff --git a/pyaedt/edb_core/edb_data/terminals.py b/pyaedt/edb_core/edb_data/terminals.py
@@ -65,6 +65,10 @@ def is_circuit_port(self):
         """Whether it is a circuit port."""
         return self._edb_object.GetIsCircuitPort()
 
+    @is_circuit_port.setter
+    def is_circuit_port(self, value):
+        self._edb_object.SetIsCircuitPort(value)
+
     @property
     def _port_post_processing_prop(self):
         """Get port post processing properties."""