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FEAT: Added new method for creating ibis circuit schematic starting f…
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…rom a list of pins in the schematic (#4937)

Co-authored-by: maxcapodi78 <Shark78>
Co-authored-by: gmalinve <[email protected]>
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@maxcapodi78 @gmalinve
maxcapodi78 and gmalinve authored Jul 22, 2024
1 parent eb9f171 commit af937c3
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Showing 7 changed files with 470 additions and 139 deletions.
42 changes: 34 additions & 8 deletions _unittest/test_21_Circuit.py
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Original file line number Diff line number Diff line change
Expand Up @@ -169,6 +169,8 @@ def test_11_export_fullwave(self):

def test_12_connect_components(self):
myind = self.aedtapp.modeler.schematic.create_inductor("L100", 1e-9)
myind2 = self.aedtapp.modeler.schematic.create_inductor("L1001", 1e-9)
myind3 = self.aedtapp.modeler.schematic.create_inductor("L1002", 1e-9)
myres = self.aedtapp.modeler.schematic.create_resistor("R100", 50)
mycap = self.aedtapp.modeler.schematic.create_capacitor("C100", 1e-12)
portname = self.aedtapp.modeler.schematic.create_interface_port("Port1")
Expand All @@ -177,6 +179,9 @@ def test_12_connect_components(self):
assert myind.pins[0].connect_to_component(portname.pins[0])
assert myind.pins[1].connect_to_component(myres.pins[1], use_wire=True)
assert self.aedtapp.modeler.connect_schematic_components(myres.id, mycap.id, pin_starting=1)
assert self.aedtapp.modeler.connect_schematic_components(
myind2, myind3, pin_starting=["n1", "n2"], pin_ending=["n2", "n1"], use_wire=False
)
gnd = self.aedtapp.modeler.schematic.create_gnd()
assert mycap.pins[1].connect_to_component(gnd.pins[0])
# create_interface_port
Expand Down Expand Up @@ -888,8 +893,8 @@ def test_48_automatic_tdr(self):

result, tdr_probe_name = self.aedtapp.create_tdr_schematic_from_snp(
input_file=touchstone_file,
probe_pins=["A-MII-RXD1_30.SQFP28X28_208.P"],
probe_ref_pins=["A-MII-RXD1_65.SQFP20X20_144.N"],
tx_schematic_pins=["A-MII-RXD1_30.SQFP28X28_208.P"],
tx_schematic_differential_pins=["A-MII-RXD1_65.SQFP20X20_144.N"],
termination_pins=["A-MII-RXD2_32.SQFP28X28_208.P", "A-MII-RXD2_66.SQFP20X20_144.N"],
differential=True,
rise_time=35,
Expand All @@ -905,14 +910,13 @@ def test_49_automatic_ami(self):
ami_file = os.path.join(local_path, "example_models", test_subfolder, "pcieg5_32gt.ibs")
result, eye_curve_tx, eye_curve_rx = self.aedtapp.create_ami_schematic_from_snp(
input_file=touchstone_file,
ibis_ami=ami_file,
component_name="Spec_Model",
ibis_tx_file=ami_file,
tx_buffer_name="1p",
rx_buffer_name="2p",
tx_pins=["A-MII-RXD1_30.SQFP28X28_208.P"],
tx_refs=["A-MII-RXD1_65.SQFP20X20_144.N"],
rx_pins=["A-MII-RXD2_32.SQFP28X28_208.P"],
rx_refs=["A-MII-RXD2_66.SQFP20X20_144.N"],
tx_schematic_pins=["A-MII-RXD1_30.SQFP28X28_208.P"],
rx_schematic_pins=["A-MII-RXD2_32.SQFP28X28_208.P"],
tx_schematic_differential_pins=["A-MII-RXD1_65.SQFP20X20_144.N"],
rx_schematic_differentialial_pins=["A-MII-RXD2_66.SQFP20X20_144.N"],
use_ibis_buffer=False,
differential=True,
bit_pattern="random_bit_count=2.5e3 random_seed=1",
Expand All @@ -923,6 +927,28 @@ def test_49_automatic_ami(self):
)
assert result

@pytest.mark.skipif(config["NonGraphical"] and is_linux, reason="Method not working in Linux and Non graphical.")
def test_49_automatic_ibis(self):
touchstone_file = os.path.join(local_path, "example_models", test_subfolder, touchstone_custom)
ibis_file = os.path.join(local_path, "example_models", "T15", "u26a_800_modified.ibs")
result, eye_curve_tx, eye_curve_rx = self.aedtapp.create_ibis_schematic_from_snp(
input_file=touchstone_file,
ibis_tx_file=ibis_file,
tx_buffer_name="DQ_FULL_800",
rx_buffer_name="DQ_FULL_800",
tx_schematic_pins=["A-MII-RXD1_30.SQFP28X28_208.P"],
rx_schematic_pins=["A-MII-RXD2_32.SQFP28X28_208.P"],
ibis_rx_file=ibis_file,
use_ibis_buffer=True,
differential=False,
bit_pattern="random_bit_count=2.5e3 random_seed=1",
unit_interval="31.25ps",
use_convolution=True,
analyze=False,
design_name="AMI",
)
assert result

def test_50_enforce_touchstone_passive(self):
self.aedtapp.insert_design("Touchstone_passive")
self.aedtapp.modeler.schematic_units = "mil"
Expand Down
24 changes: 14 additions & 10 deletions examples/07-Circuit/Virtual_Compliance.py
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Original file line number Diff line number Diff line change
Expand Up @@ -92,8 +92,8 @@
# The original circuit schematic is duplicated and modified to achieve this target.

result, tdr_probe_name = cir.create_tdr_schematic_from_snp(input_file=touchstone_path,
probe_pins=["X1.A2.PCIe_Gen4_RX0_P"],
probe_ref_pins=["X1.A3.PCIe_Gen4_RX0_N"],
tx_schematic_pins=["X1.A2.PCIe_Gen4_RX0_P"],
tx_schematic_differential_pins=["X1.A3.PCIe_Gen4_RX0_N"],
termination_pins=["U1.AP26.PCIe_Gen4_RX0_P",
"U1.AN26.PCIe_Gen4_RX0_N"],
differential=True, rise_time=35, use_convolution=True,
Expand All @@ -105,14 +105,18 @@
# Create an Ibis AMI project to compute an eye diagram simulation and retrieve
# eye mask violations.
result, eye_curve_tx, eye_curve_rx = cir.create_ami_schematic_from_snp(input_file=touchstone_path,
ibis_ami=os.path.join(projectdir, "models",
"pcieg5_32gt.ibs"),
component_name="Spec_Model", tx_buffer_name="1p",
rx_buffer_name="2p",
tx_pins=["U1.AM25.PCIe_Gen4_TX0_CAP_P"],
tx_refs=["U1.AL25.PCIe_Gen4_TX0_CAP_N"],
rx_pins=["X1.B2.PCIe_Gen4_TX0_P"],
rx_refs=["X1.B3.PCIe_Gen4_TX0_N"],
ibis_tx_file=os.path.join(projectdir, "models",
"pcieg5_32gt.ibs"),
tx_buffer_name="1p", rx_buffer_name="2p",
tx_schematic_pins=[
"U1.AM25.PCIe_Gen4_TX0_CAP_P"],
rx_schematic_pins=[
"X1.B2.PCIe_Gen4_TX0_P"],
tx_schematic_differential_pins=[
"U1.AL25.PCIe_Gen4_TX0_CAP_N"],
rx_schematic_differentialial_pins=[
"X1.B3.PCIe_Gen4_TX0_N"],
ibis_tx_component_name="Spec_Model",
use_ibis_buffer=False, differential=True,
bit_pattern="random_bit_count=2.5e3 random_seed=1",
unit_interval="31.25ps", use_convolution=True,
Expand Down
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