Cleanup examples (remove unused imports and fix typos) (#4038)

* Fix typos. * Remove unused import from examples. * Update examples/02-SBR+/SBR_Example.py
ansys · Jan 9, 2024 · f2dab43 · f2dab43
1 parent ffcf970
commit f2dab43
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Showing 13 changed files with 7 additions and 15 deletions.
diff --git a/doc/source/conf.py b/doc/source/conf.py
@@ -277,7 +277,7 @@ def setup(app):
             "examples_dirs": ["../../examples/"],
             # path where to save gallery generated examples
             "gallery_dirs": ["examples"],
-            # Patter to search for examples files
+            # Pattern to search for examples files
             "filename_pattern": r"\.py",
             # Remove the "Download all examples" button from the top level gallery
             "download_all_examples": False,

diff --git a/examples/00-EDB/01_edb_example.py b/examples/00-EDB/01_edb_example.py
@@ -8,8 +8,6 @@
 # ~~~~~~~~~~~~~~~~~~~~~~~~
 # Perform required imports.
 
-import shutil
-
 import os
 import time
 import pyaedt

diff --git a/examples/00-EDB/10_GDS_workflow.py b/examples/00-EDB/10_GDS_workflow.py
@@ -33,7 +33,7 @@
 # ~~~~~~~~~~~~
 # A Control file is an xml file which purpose if to provide additional
 # information during import phase. It can include, materials, stackup, setup, boundaries and settings.
-# In this example we will import an exising xml, integrate it with a layer mapping file of gds
+# In this example we will import an existing xml, integrate it with a layer mapping file of gds
 # and then adding setup and boundaries.
 
 c = ControlFile(c_file_in, layer_map=c_map)

diff --git a/examples/02-SBR+/SBR_Example.py b/examples/02-SBR+/SBR_Example.py
@@ -7,7 +7,7 @@
 ###############################################################################
 # Perform required imports
 # ~~~~~~~~~~~~~~~~~~~~~~~~
-# Perrform rquired imports and set up the local path to the path for the PyAEDT
+# Perform required imports and set up the local path to the path for the PyAEDT
 # directory.
 
 import os

diff --git a/examples/02-SBR+/SBR_Time_Plot.py b/examples/02-SBR+/SBR_Time_Plot.py
@@ -8,7 +8,7 @@
 ###############################################################################
 # Perform required imports.
 # ~~~~~~~~~~~~~~~~~~~~~~~~~
-# Perform requried imports.
+# Perform required imports.
 
 import os
 from pyaedt import Hfss, downloads

diff --git a/examples/03-Maxwell/Maxwell3DTeam7.py b/examples/03-Maxwell/Maxwell3DTeam7.py
@@ -1,7 +1,7 @@
 """
 Maxwell 3D: asymmetric conductor analysis
 -----------------------------------------
-This example uses PyAEDT to set up the TEAM 7 problem for an asymetric
+This example uses PyAEDT to set up the TEAM 7 problem for an asymmetric
 conductor with a hole and solve it using the Maxwell 3D Eddy Current solver.
 """
 ###########################################################################################

diff --git a/examples/04-Icepak/Icepak_ECAD_Import.py b/examples/04-Icepak/Icepak_ECAD_Import.py
@@ -62,7 +62,7 @@
 #    :alt: LDF image.
 #
 #
-# Imports the idf files with several filtering options incluing caps, resistors, inductors, power, size, ...
+# Imports the idf files with several filtering options including caps, resistors, inductors, power, size, ...
 # There are also options for the PCB creation (number o flayers, copper percentages, layer sizes). 
 # In this examples, the default values are used for the PCB.
 # The imported PCB here will be deleted later and replaced by a PCB that has the trace information for higher accuracy.

diff --git a/examples/05-Q3D/Q3D_DC_IR.py b/examples/05-Q3D/Q3D_DC_IR.py
@@ -10,7 +10,6 @@
 # ~~~~~~~~~~~~~~~~~~~~~~~~
 # Perform required imports.
 import os
-import tempfile
 import pyaedt
 
 

diff --git a/examples/05-Q3D/Q3D_from_EDB.py b/examples/05-Q3D/Q3D_from_EDB.py
@@ -10,7 +10,6 @@
 # ~~~~~~~~~~~~~~~~~~~~~~~~
 # Perform required imports.
 import os
-import tempfile
 import pyaedt
 
 

diff --git a/examples/07-Circuit/Circuit_Example.py b/examples/07-Circuit/Circuit_Example.py
@@ -12,7 +12,6 @@
 # sphinx_gallery_thumbnail_path = 'Resources/circuit.png'
 
 import pyaedt
-import os
 
 ###############################################################################
 # Launch AEDT

diff --git a/examples/07-TwinBuilder/01-RC_Circuit_Example.py b/examples/07-TwinBuilder/01-RC_Circuit_Example.py
@@ -10,7 +10,6 @@
 # ~~~~~~~~~~~~~~~~~~~~~~~~
 # Perform required imports.
 
-import os
 import pyaedt
 
 ###############################################################################

diff --git a/examples/07-TwinBuilder/02-Wiring_A_Rectifier.py b/examples/07-TwinBuilder/02-Wiring_A_Rectifier.py
@@ -10,7 +10,6 @@
 # ~~~~~~~~~~~~~~~~~~~~~~~~
 # Perform required imports.
 
-import os
 import math
 import matplotlib.pyplot as plt
 import pyaedt

diff --git a/examples/07-TwinBuilder/03-Dynamic_ROM_Creation_And_Visualization.py b/examples/07-TwinBuilder/03-Dynamic_ROM_Creation_And_Visualization.py
@@ -15,7 +15,6 @@
 # Perform required imports.
 
 import os
-import math
 import shutil
 import matplotlib.pyplot as plt
 from pyaedt import TwinBuilder
@@ -85,7 +84,7 @@
 conf_file_path = os.path.join(data_folder,source_build_conf_file)
 dynamic_rom_builder.Build(conf_file_path.replace('\\', '/'))
 
-# Test if ROM was created sucessfully
+# Test if ROM was created successfully
 dynamic_rom_path = os.path.join(data_folder,'DynamicRom.dyn')
 if os.path.exists(dynamic_rom_path):
 	tb._odesign.AddMessage("Info","path exists: {}".format(dynamic_rom_path.replace('\\', '/')), "")