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fs_inode:Change the type of i_crefs to atomic_int
Summary: 1.Modified the i_crefs from int16_t to atomic_int 2.Modified the i_crefs add, delete, read, and initialize interfaces to atomic operations The purpose of this change is to avoid deadlock in cross-core scenarios, where A Core blocks B Core’s request for a write operation to A Core when A Core requests a read operation to B Core. Signed-off-by: chenrun1 <[email protected]>
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@xiaoxiang781216 @crafcat7
We got the trouble by this PR.
Our platform does not support the atomic instruction although our platfom uses Cortex-M4F.
Of course our CM4F can execute the atomic instruction,
but our platform does not implement the monitor for exclusive access which is described in ARMv7-M Architecture Reference Manual,
and our platform alwas returns the result of atomic instruction as fail.
So this PR will make an inifite loop at our platform,
we use the primask insted of the atomic instruction because our platform is an uniprocessor.
I think the processor which compliants with ARMv7-M is not enough to support the atomic instruction,
it is also needed to implement the monitor for exclusive access.
Please take care for such platform, althogh it might be rare case.
To avoid using the atomic instruction on above platform,
How about following idea?
All functions which are described in arch_atomic.c must be needed to rename other than the name of atomic functions. (ex : atomic_fetch_add -> nx_atomic_fetch_add)
Include "include/nuttx/lib/stdatomic.h" which defines atomic_fetch_add -> nx_atomic_fetch_add.
I think
these atomic functions are implemented as built-in function at GCC, built-in functions are inlined when the source codes are compiled,
to avoid using built-in functions, not to call them.
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@crafcat7 will provide a patch, please try it.
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Hi,I have provided a patch here #14537, which is used to determine whether to use the toolchain's atomic by checking the macro.
In https://en.cppreference.com/w/c/atomic it is mentioned
For your situation, I think it is possible to solve it by adding the STDC_NO_ATOMICS flag on this basis.
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#14537 (comment) Continue this discussion.
Hi, What I want to ask is whether we can make it work in arch_atomic based on the changes in PR #14537 by adding FLAGS += STDC_NO_ATOMICS in the compilation options of this soc?
I think as long as it declares STDC_NO_ATOMICS, then it will be pointed to arch_atomic
https://github.com/apache/nuttx/pull/14537/files#diff-83e77068636671f3a69415d40cc75ba82be4a8f1eb2e02cfd44b60ae7a32998cR78-R80
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Yes, of course.
@crafcat7 please compile on M4/M7/M33/M55 device and compare the dissemble code to find the best method.
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I tried it on our local stm32-tiny (M3) and FRDM-k64f (M4). Normally, it compiles and connects to the method provided by the toolchain.
I executed the test cases of apps/testing/atomic in the FRDM-K64F environment, and the results were correct
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@TakuyaMiyasita could you provide the toolchain/version, command line you use and the dissemble output? The local monitor inside cpu core is enough to make ldrex/strex work for UP case, I think.
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@xiaoxiang781216 @crafcat7
Thank you for your concern.
the toolchain version is here.
and the part of disassemble code is here.
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so, the compiler generates the exclusive load/store:
but your chip fail to run it correctly.
The following modification is needed for your chip:
could you provide a PR?
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@xiaoxiang781216
I will try it.