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[Mellanox][202311] Adding SKU Mellanox-SN4700-O32 and Mellanox-SN4700-V64 #42
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15 changes: 15 additions & 0 deletions
15
device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/buffers.json.j2
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{# | ||
Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. | ||
Apache-2.0 | ||
Licensed under the Apache License, Version 2.0 (the "License"); | ||
you may not use this file except in compliance with the License. | ||
You may obtain a copy of the License at | ||
http://www.apache.org/licenses/LICENSE-2.0 | ||
Unless required by applicable law or agreed to in writing, software | ||
distributed under the License is distributed on an "AS IS" BASIS, | ||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
See the License for the specific language governing permissions and | ||
limitations under the License. | ||
#} | ||
{%- set default_topo = 't1' %} | ||
{%- include 'buffers_config.j2' %} |
1 change: 1 addition & 0 deletions
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/buffers_defaults_objects.j2
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../../x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/buffers_defaults_objects.j2 |
36 changes: 36 additions & 0 deletions
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/buffers_defaults_t0.j2
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{# | ||
Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. | ||
Apache-2.0 | ||
Licensed under the Apache License, Version 2.0 (the "License"); | ||
you may not use this file except in compliance with the License. | ||
You may obtain a copy of the License at | ||
http://www.apache.org/licenses/LICENSE-2.0 | ||
Unless required by applicable law or agreed to in writing, software | ||
distributed under the License is distributed on an "AS IS" BASIS, | ||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
See the License for the specific language governing permissions and | ||
limitations under the License. | ||
#} | ||
{% set default_cable = '5m' %} | ||
{% set ingress_lossless_pool_size = '51806208' %} | ||
{% set ingress_lossless_pool_xoff = '3407872' %} | ||
{% set egress_lossless_pool_size = '60817392' %} | ||
{% set egress_lossy_pool_size = '51806208' %} | ||
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||
{% import 'buffers_defaults_objects.j2' as defs with context %} | ||
|
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{%- macro generate_buffer_pool_and_profiles_with_inactive_ports(port_names_inactive) %} | ||
{{ defs.generate_buffer_pool_and_profiles_with_inactive_ports(port_names_inactive) }} | ||
{%- endmacro %} | ||
|
||
{%- macro generate_profile_lists_with_inactive_ports(port_names_active, port_names_inactive) %} | ||
{{ defs.generate_profile_lists(port_names_active, port_names_inactive) }} | ||
{%- endmacro %} | ||
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||
{%- macro generate_queue_buffers_with_inactive_ports(port_names_active, port_names_inactive) %} | ||
{{ defs.generate_queue_buffers(port_names_active, port_names_inactive) }} | ||
{%- endmacro %} | ||
|
||
{%- macro generate_pg_profiles_with_inactive_ports(port_names_active, port_names_inactive) %} | ||
{{ defs.generate_pg_profiles(port_names_active, port_names_inactive) }} | ||
{%- endmacro %} |
37 changes: 37 additions & 0 deletions
37
device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/buffers_defaults_t1.j2
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{# | ||
Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. | ||
Apache-2.0 | ||
Licensed under the Apache License, Version 2.0 (the "License"); | ||
you may not use this file except in compliance with the License. | ||
You may obtain a copy of the License at | ||
http://www.apache.org/licenses/LICENSE-2.0 | ||
Unless required by applicable law or agreed to in writing, software | ||
distributed under the License is distributed on an "AS IS" BASIS, | ||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
See the License for the specific language governing permissions and | ||
limitations under the License. | ||
#} | ||
{% set default_cable = '40m' %} | ||
{% set ingress_lossless_pool_size = '45531136' %} | ||
{% set ingress_lossless_pool_xoff = '9682944' %} | ||
{% set egress_lossless_pool_size = '60817392' %} | ||
{% set egress_lossy_pool_size = '45531136' %} | ||
|
||
|
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{% import 'buffers_defaults_objects.j2' as defs with context %} | ||
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{%- macro generate_buffer_pool_and_profiles_with_inactive_ports(port_names_inactive) %} | ||
{{ defs.generate_buffer_pool_and_profiles_with_inactive_ports(port_names_inactive) }} | ||
{%- endmacro %} | ||
|
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{%- macro generate_profile_lists_with_inactive_ports(port_names_active, port_names_inactive) %} | ||
{{ defs.generate_profile_lists(port_names_active, port_names_inactive) }} | ||
{%- endmacro %} | ||
|
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{%- macro generate_queue_buffers_with_inactive_ports(port_names_active, port_names_inactive) %} | ||
{{ defs.generate_queue_buffers(port_names_active, port_names_inactive) }} | ||
{%- endmacro %} | ||
|
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{%- macro generate_pg_profiles_with_inactive_ports(port_names_active, port_names_inactive) %} | ||
{{ defs.generate_pg_profiles(port_names_active, port_names_inactive) }} | ||
{%- endmacro %} |
16 changes: 16 additions & 0 deletions
16
device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/buffers_dynamic.json.j2
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{# | ||
Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. | ||
Apache-2.0 | ||
Licensed under the Apache License, Version 2.0 (the "License"); | ||
you may not use this file except in compliance with the License. | ||
You may obtain a copy of the License at | ||
http://www.apache.org/licenses/LICENSE-2.0 | ||
Unless required by applicable law or agreed to in writing, software | ||
distributed under the License is distributed on an "AS IS" BASIS, | ||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
See the License for the specific language governing permissions and | ||
limitations under the License. | ||
#} | ||
{%- set default_topo = 't1' %} | ||
{%- set dynamic_mode = 'true' %} | ||
{%- include 'buffers_config.j2' %} |
132 changes: 132 additions & 0 deletions
132
device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/hwsku.json
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{ | ||
"interfaces": { | ||
"Ethernet0": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet8": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet16": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet24": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet32": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet40": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet48": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet56": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet64": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet72": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet80": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet88": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet96": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet104": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet112": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet120": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet128": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet136": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet144": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet152": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet160": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet168": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet176": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet184": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet192": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet200": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet208": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet216": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet224": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet232": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet240": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
}, | ||
"Ethernet248": { | ||
"default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
"autoneg": "off" | ||
} | ||
} | ||
} |
1 change: 1 addition & 0 deletions
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/media_settings.json
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../Mellanox-SN4700-O8C48/media_settings.json |
1 change: 1 addition & 0 deletions
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/optics_si_settings.json
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../Mellanox-SN4700-O8C48/optics_si_settings.json |
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/pg_profile_lookup.ini
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## | ||
## Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. | ||
## Apache-2.0 | ||
## | ||
## Licensed under the Apache License, Version 2.0 (the "License"); | ||
## you may not use this file except in compliance with the License. | ||
## You may obtain a copy of the License at | ||
## | ||
## http://www.apache.org/licenses/LICENSE-2.0 | ||
## | ||
## Unless required by applicable law or agreed to in writing, software | ||
## distributed under the License is distributed on an "AS IS" BASIS, | ||
## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
## See the License for the specific language governing permissions and | ||
## limitations under the License. | ||
## | ||
# PG lossless profiles. | ||
# speed cable size xon xoff threshold | ||
10000 5m 19456 19456 16384 0 | ||
25000 5m 19456 19456 17408 0 | ||
40000 5m 19456 19456 19456 0 | ||
50000 5m 19456 19456 21504 0 | ||
100000 5m 19456 19456 37888 0 | ||
200000 5m 19456 19456 43008 0 | ||
400000 5m 38912 38912 73728 0 | ||
10000 40m 19456 19456 16384 0 | ||
25000 40m 19456 19456 18432 0 | ||
40000 40m 19456 19456 21504 0 | ||
50000 40m 19456 19456 23552 0 | ||
100000 40m 19456 19456 43008 0 | ||
200000 40m 19456 19456 51200 0 | ||
400000 40m 38912 38912 91136 0 | ||
10000 300m 19456 19456 19456 0 | ||
25000 300m 19456 19456 26624 0 | ||
40000 300m 19456 19456 34816 0 | ||
50000 300m 19456 19456 40960 0 | ||
100000 300m 19456 19456 75776 0 | ||
200000 300m 19456 19456 118784 0 | ||
400000 300m 38912 38912 225280 0 | ||
10000 1500m 19456 19456 35840 0 | ||
25000 1500m 19456 19456 65536 0 | ||
40000 1500m 19456 19456 96256 0 | ||
50000 1500m 19456 19456 117760 0 | ||
100000 1500m 19456 19456 230400 0 | ||
200000 1500m 19456 19456 427008 0 | ||
400000 1500m 38912 38912 427008 0 | ||
10000 2000m 19456 19456 41984 0 | ||
25000 2000m 19456 19456 80896 0 | ||
40000 2000m 19456 19456 121856 0 | ||
50000 2000m 19456 19456 149504 0 | ||
100000 2000m 19456 19456 293888 0 | ||
200000 2000m 19456 19456 555008 0 | ||
400000 2000m 38912 38912 555008 0 |
6 changes: 6 additions & 0 deletions
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/pmon_daemon_control.json
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{ | ||
"skip_ledd": true, | ||
"skip_fancontrol": true, | ||
"skip_xcvrd_cmis_mgr": false | ||
} | ||
|
1 change: 1 addition & 0 deletions
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/port_config.ini
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../ACS-MSN4700/port_config.ini |
1 change: 1 addition & 0 deletions
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/qos.json.j2
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../../x86_64-mlnx_msn2700-r0/ACS-MSN2700/qos.json.j2 |
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/sai.profile
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SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_4700_32x400g.xml | ||
SAI_INDEPENDENT_MODULE_MODE=1 |
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do we need to support dual tor in 202311 for o32 t0?