Changing expect line function so that it reports previously buffered … #5998
rslawsonci.yml
on: push
Build dependencies
2m 46s
bittide-instances hardware-in-the-loop test matrix generation
18s
bittide-instances synthesis matrix generation
19s
bittide-experiments unittests
1m 1s
Bittide tests
7m 28s
Rust Lints
1m 12s
Firmware Support Unit Tests
3m 17s
Host Tools Unit Tests
45s
Firmware Limit Checks
41s
bittide-instances doctests
55s
bittide-instances unittests
1m 36s
Matrix: synth
Matrix: HITL
All jobs finished
5s
Annotations
3 errors and 1 warning
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HITL (vexRiscvTcpTest, test)
Process completed with exit code 1.
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HITL (vexRiscvTest, test)
Process completed with exit code 1.
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All jobs finished
Process completed with exit code 1.
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HITL (linkConfigurationTest, test)
No files were found with the provided path: _build/vivado/*/ila-data
_build/hitl/*. No artifacts will be uploaded.
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Artifacts
Produced during runtime
| Name | Size | |
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_build-fullMeshHwCcTest
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130 MB |
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_build-fullMeshHwCcTest-debug
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4.24 MB |
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_build-fullMeshSwCcTest
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272 MB |
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_build-fullMeshSwCcTest-debug
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3.92 MB |
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_build-linkConfigurationTest
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12.4 MB |
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_build-safeDffSynchronizer
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2.58 KB |
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_build-transceiversUpTest
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192 MB |
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_build-transceiversUpTest-debug
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1.96 MB |
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_build-vexRiscvTcpTest
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48.1 MB |
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_build-vexRiscvTcpTest-debug
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22 KB |
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_build-vexRiscvTest
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40 MB |
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_build-vexRiscvTest-debug
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22 KB |
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