Remove unused clock configuration #4656
ci.yml
on: push
Build dependencies
2m 41s
Basic linting
16s
cc-sim-topologies simulation matrix generation
26s
bittide-instances hardware-in-the-loop test matrix generation
30s
bittide-instances synthesis matrix generation
29s
Rust Lints
48s
Firmware Support Unit Tests
2m 23s
Host Tools Unit Tests
38s
Firmware Limit Checks
44s
bittide-experiments unittests
49s
Bittide tests
5m 42s
bittide-instances doctests
50s
bittide-instances unittests
1m 9s
Matrix: Simulate network
Matrix: synth
Matrix: HITL
All jobs finished
3s
Annotations
2 errors
Generate clock control simulation report
Process completed with exit code 1.
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All jobs finished
Process completed with exit code 1.
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Artifacts
Produced during runtime
Name | Size | |
---|---|---|
_build-fincFdecTests
Expired
|
19.6 MB |
|
_build-fincFdecTests-debug
Expired
|
8.49 MB |
|
gen-plots-hs-complete
Expired
|
52.7 KB |
|