Retry with xilix clock networks

bittide · Nov 7, 2024 · 3cf4280 · 3cf4280
1 parent 26ddaf0
commit 3cf4280
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/bittide/src/Clash/Cores/Xilinx/GTHnew/Internal.hs b/bittide/src/Clash/Cores/Xilinx/GTHnew/Internal.hs
@@ -193,10 +193,10 @@ gthCore
       , rxctrl3_out
       )
  where
-  (txUsrClk,txUsrClk2,txUsrClkActive) = gthUserClockNetwork txoutclk_out txUsrClkRst
-  (rxUsrClk,rxUsrClk2,rxUsrClkActive) = gthUserClockNetwork rxoutclk_out rxUsrClkRst
-  -- (txUsrClk,txUsrClk2,txUsrClkActive) = xilinxGthUserClockNetworkTx txoutclk_out txUsrClkRst
-  -- (rxUsrClk,rxUsrClk2,rxUsrClkActive) = xilinxGthUserClockNetworkRx rxoutclk_out rxUsrClkRst
+  -- (txUsrClk,txUsrClk2,txUsrClkActive) = gthUserClockNetwork txoutclk_out txUsrClkRst
+  -- (rxUsrClk,rxUsrClk2,rxUsrClkActive) = gthUserClockNetwork rxoutclk_out rxUsrClkRst
+  (txUsrClk,txUsrClk2,txUsrClkActive) = xilinxGthUserClockNetworkTx txoutclk_out txUsrClkRst
+  (rxUsrClk,rxUsrClk2,rxUsrClkActive) = xilinxGthUserClockNetworkRx rxoutclk_out rxUsrClkRst
   txUsrClkRst = noReset @txUser2
   -- txUsrClkRst = unsafeFromActiveLow $ fmap bitCoerce txpmaresetdone
   rxUsrClkRst = noReset @rxUser2