Split ILA capture in separate capture conditions

bittide · Jun 12, 2024 · f4be4a6 · f4be4a6
1 parent aee9c10
commit f4be4a6
Showing 1 changed file with 41 additions and 14 deletions.
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/FincFdec.hs b/bittide-instances/src/Bittide/Instances/Hitl/FincFdec.hs
@@ -288,20 +288,43 @@ fincFdecTests diffClk controlledDiffClock spiIn =
   onChange :: (HiddenClockResetEnable dom, Eq a, NFDataX a) => Signal dom a -> Signal dom Bool
   onChange x = (Just <$> x) ./=. register hasClock hasReset hasEnable Nothing (Just <$> x)
 
-  capture :: Signal Basic125 Bool
-  capture =
-    withClockResetEnable clk clkStableRst enableGen $
-    onChange $ bundle
-      ( testInput
-      , testDone
-      , testSuccess
-      , (xpmCdcSingle txClock clk txActive)
-      , nettoFincs
-      , spiBusy
-      , (slice d39 d36 . pack <$> spiState) -- Constructor bits
-      , spiDone
-      , diffCounterActive
+  captureCond :: Signal Basic125 (Vec 4 Bool)
+  captureCond =
+    bundle
+      (  captureResets
+      :> captureSpiState
+      :> captureTestState
+      :> captureDomainDiff
+      :> Nil
       )
+   where
+    captureSpiState :: Signal Basic125 Bool
+    captureSpiState =
+      spiBusy .&&.
+      (withClockResetEnable clk clkStableRst enableGen $
+        onChange (slice d39 d36 . pack <$> spiState))
+
+    captureTestState :: Signal Basic125 Bool
+    captureTestState =
+      withClockResetEnable clk clkStableRst enableGen $
+        onChange (bundle (testInput, testDone, testSuccess))
+
+    captureDomainDiff :: Signal Basic125 Bool
+    captureDomainDiff =
+      spiDone .&&. (abs (diffCounter - lastSample) .>=. 8)
+     where
+      lastSample = regEn clk clkStableRst enableGen 0 captureDomainDiff diffCounter
+
+    captureResets :: Signal Basic125 Bool
+    captureResets =
+      withClockResetEnable clk clkStableRst enableGen $
+        onChange $ bundle
+          ( spiDone
+          , init_done
+          , xpmCdcSingleWith cdcConfig txClock clk $ unpack <$> reset_tx_done :: Signal Basic125 Bool
+          , xpmCdcSingleWith cdcConfig txClock clk $ unpack <$> txActive :: Signal Basic125 Bool
+          , unsafeToActiveHigh reset_all_out_sig
+          )
 
   fincFdecIla :: Signal Basic125 ()
   fincFdecIla = setName @"fincFdecIla" $ ila
@@ -312,6 +335,7 @@ fincFdecTests diffClk controlledDiffClock spiIn =
       :> "testDone"
       :> "testSuccess"
       :> "reset_all_out_sig"
+      :> "reset_tx_done"
       :> "init_done"
       :> "txActive"
       :> "spiBusy"
@@ -322,17 +346,19 @@ fincFdecTests diffClk controlledDiffClock spiIn =
       :> "diffCounter"
       :> "counterSys"
       :> "counterGht"
+      :> "condition"
       :> Nil
     ){depth = D65536}
     clk
     -- Trigger on when the system clock becomes stable
     (unsafeToActiveLow clkStableRst)
-    capture
+    (fmap or captureCond)
     -- Debug probes
     testInput
     testDone
     testSuccess
     (unsafeToActiveHigh reset_all_out_sig)
+    (xpmCdcSingleWith cdcConfig txClock clk $ unpack <$> reset_tx_done :: Signal Basic125 Bool)
     init_done
     (xpmCdcSingleWith cdcConfig txClock clk $ unpack <$> txActive :: Signal Basic125 Bool)
     spiBusy
@@ -343,6 +369,7 @@ fincFdecTests diffClk controlledDiffClock spiIn =
     diffCounter
     counterSys
     counterGht
+    captureCond
 
   testInput :: Signal Basic125 (Maybe Test)
   testInput = hitlVio FDec clk testDone testSuccess