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Use HAL's radio clock control (esp-rs#153)
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@bjoernQ
bjoernQ committed May 23, 2024
1 parent c58a8bb commit c2f7ad4
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Showing 18 changed files with 100 additions and 656 deletions.
18 changes: 1 addition & 17 deletions esp-wifi/src/ble/os_adapter_esp32.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -311,23 +311,7 @@ pub(crate) fn btdm_controller_mem_init() {
}

pub(crate) fn bt_periph_module_enable() {
unsafe {
const DR_REG_DPORT_BASE: u32 = 0x3ff00000;
const DPORT_WIFI_CLK_EN_REG: u32 = DR_REG_DPORT_BASE + 0x0CC;
const DPORT_CORE_RST_EN_REG: u32 = DR_REG_DPORT_BASE + 0x0D0;
const DPORT_WIFI_CLK_BT_EN: u32 = 0x30800;

let ptr = DPORT_WIFI_CLK_EN_REG as *mut u32;
let old = ptr.read_volatile();
ptr.write_volatile(old | DPORT_WIFI_CLK_BT_EN);

let ptr = DPORT_CORE_RST_EN_REG as *mut u32;
let old = ptr.read_volatile();
ptr.write_volatile(old | 0);
}
// bt_periph_module_enable(PERIPH_BT_MODULE);
// modifyreg32(get_clk_en_reg(periph), 0, get_clk_en_mask(periph));
// modifyreg32(get_rst_en_reg(periph), get_rst_en_mask(periph, true), 0);
// nothing
}

pub(crate) fn disable_sleep_mode() {
Expand Down
113 changes: 7 additions & 106 deletions esp-wifi/src/ble/os_adapter_esp32c2.rs
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Original file line number Diff line number Diff line change
@@ -1,4 +1,6 @@
use crate::binary::include::esp_bt_controller_config_t;
use crate::common_adapter::RADIO_CLOCKS;
use crate::hal::system::RadioClockController;

pub(crate) static mut ISR_INTERRUPT_4: (
*mut crate::binary::c_types::c_void,
Expand Down Expand Up @@ -96,115 +98,14 @@ pub(super) unsafe extern "C" fn esp_intr_alloc(
}

pub(super) fn ble_rtc_clk_init() {
/*
// modem_clkrst_reg
// LP_TIMER_SEL_XTAL32K -> 0
// LP_TIMER_SEL_XTAL -> 1
// LP_TIMER_SEL_8M -> 0
// LP_TIMER_SEL_RTC_SLOW -> 0
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_8M_S);
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
#ifdef CONFIG_XTAL_FREQ_26
// LP_TIMER_CLK_DIV_NUM -> 130
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 129, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
#else
// LP_TIMER_CLK_DIV_NUM -> 250
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
#endif // CONFIG_XTAL_FREQ_26
// MODEM_CLKRST_ETM_CLK_ACTIVE -> 1
// MODEM_CLKRST_ETM_CLK_SEL -> 0
SET_PERI_REG_BITS(MODEM_CLKRST_ETM_CLK_CONF_REG, 1, 1, MODEM_CLKRST_ETM_CLK_ACTIVE_S);
SET_PERI_REG_BITS(MODEM_CLKRST_ETM_CLK_CONF_REG, 1, 0, MODEM_CLKRST_ETM_CLK_SEL_S);
*/

const MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG: u32 = DR_REG_MODEM_CLKRST_BASE + 0x4;
const DR_REG_MODEM_CLKRST_BASE: u32 = 0x6004d800;
const MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S: u32 = 3;
const MODEM_CLKRST_LP_TIMER_SEL_XTAL_S: u32 = 2;
const MODEM_CLKRST_LP_TIMER_SEL_8M_S: u32 = 1;
const MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S: u32 = 0;
const MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM: u32 = 0x000000FF;
const MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S: u32 = 4;
const MODEM_CLKRST_ETM_CLK_CONF_REG: u32 = DR_REG_MODEM_CLKRST_BASE + 0x10;
const MODEM_CLKRST_ETM_CLK_ACTIVE_S: u32 = 1;
const MODEM_CLKRST_ETM_CLK_SEL_S: u32 = 0;

#[inline(always)]
fn set_peri_reg_bits(reg: u32, bit_map: u32, value: u32, shift: u32) {
let ptr = reg as *mut u32;
unsafe {
ptr.write_volatile(
ptr.read_volatile() & (!((bit_map) << (shift)))
| (((value) & (bit_map)) << (shift)),
);
}
unsafe {
RADIO_CLOCKS.as_mut().unwrap().ble_rtc_clk_init();
}

set_peri_reg_bits(
MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG,
1,
0,
MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S,
);
set_peri_reg_bits(
MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG,
1,
1,
MODEM_CLKRST_LP_TIMER_SEL_XTAL_S,
);
set_peri_reg_bits(
MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG,
1,
0,
MODEM_CLKRST_LP_TIMER_SEL_8M_S,
);
set_peri_reg_bits(
MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG,
1,
0,
MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S,
);

// assume 40MHz xtal
set_peri_reg_bits(
MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG,
MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM,
249,
MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S,
);

set_peri_reg_bits(
MODEM_CLKRST_ETM_CLK_CONF_REG,
1,
1,
MODEM_CLKRST_ETM_CLK_ACTIVE_S,
);
set_peri_reg_bits(
MODEM_CLKRST_ETM_CLK_CONF_REG,
1,
0,
MODEM_CLKRST_ETM_CLK_SEL_S,
);
}

pub(super) unsafe extern "C" fn esp_reset_rpa_moudle() {
log::trace!("esp_reset_rpa_moudle");

/*
DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, BLE_RPA_REST_BIT);
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, BLE_RPA_REST_BIT);
*/
const DR_REG_SYSCON_BASE: u32 = 0x60026000;
const SYSCON_WIFI_RST_EN_REG: u32 = DR_REG_SYSCON_BASE + 0x18;
const SYSTEM_WIFI_RST_EN_REG: u32 = SYSCON_WIFI_RST_EN_REG;
const SYSTEM_CORE_RST_EN_REG: u32 = SYSTEM_WIFI_RST_EN_REG;
const BLE_RPA_REST_BIT: u32 = 1 << 27;

let ptr = SYSTEM_CORE_RST_EN_REG as *mut u32;
ptr.write_volatile(ptr.read_volatile() | BLE_RPA_REST_BIT);
ptr.write_volatile(ptr.read_volatile() & !BLE_RPA_REST_BIT);
unsafe {
RADIO_CLOCKS.as_mut().unwrap().reset_rpa();
}
}
52 changes: 8 additions & 44 deletions esp-wifi/src/common_adapter/common_adapter_esp32.rs
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,8 @@
use super::phy_init_data::PHY_INIT_DATA_DEFAULT;
use crate::binary::include::*;
use crate::common_adapter::RADIO_CLOCKS;
use crate::hal::system::RadioClockController;
use crate::hal::system::RadioPeripherals;
use atomic_polyfill::AtomicU32;
use esp32_hal::prelude::ram;
use log::trace;
Expand All @@ -13,12 +16,6 @@ static mut S_IS_PHY_REG_STORED: bool = false;
static mut PHY_ACCESS_REF: AtomicU32 = AtomicU32::new(0);
static mut PHY_CLOCK_ENABLE_REF: AtomicU32 = AtomicU32::new(0);

// Mask for clock bits used by both WIFI and Bluetooth
const DPORT_WIFI_CLK_WIFI_BT_COMMON_M: u32 = 0x000003c9;

const DR_REG_DPORT_BASE: u32 = 0x3ff00000;
const DPORT_WIFI_CLK_EN_REG: u32 = DR_REG_DPORT_BASE + 0x0CC;

pub(crate) fn phy_mem_init() {
unsafe {
G_PHY_DIGITAL_REGS_MEM = SOC_PHY_DIG_REGS_MEM.as_ptr() as *mut u32;
Expand Down Expand Up @@ -109,9 +106,7 @@ pub(crate) unsafe fn phy_enable_clock() {
let count = PHY_CLOCK_ENABLE_REF.fetch_add(1, atomic_polyfill::Ordering::SeqCst);
if count == 0 {
critical_section::with(|_| {
let ptr = DPORT_WIFI_CLK_EN_REG as *mut u32;
let old = ptr.read_volatile();
ptr.write_volatile(old | DPORT_WIFI_CLK_WIFI_BT_COMMON_M);
RADIO_CLOCKS.as_mut().unwrap().enable(RadioPeripherals::Phy);
});
}
}
Expand All @@ -123,45 +118,14 @@ pub(crate) unsafe fn phy_disable_clock() {
let count = PHY_CLOCK_ENABLE_REF.fetch_sub(1, atomic_polyfill::Ordering::SeqCst);
if count == 1 {
critical_section::with(|_| {
let ptr = DPORT_WIFI_CLK_EN_REG as *mut u32;
let old = ptr.read_volatile();
ptr.write_volatile(old & !DPORT_WIFI_CLK_WIFI_BT_COMMON_M);
RADIO_CLOCKS
.as_mut()
.unwrap()
.disable(RadioPeripherals::Phy);
});
}
}

#[ram]
pub(crate) fn init_clocks() {
unsafe {
let mut regval = getreg32(0x6001f048); /* DR_REG_BB_BASE+48 */
regval &= !(1 << 14);
putreg32(regval, 0x6001f048);
}
}

#[inline(always)]
unsafe fn putreg32(v: u32, r: u32) {
(r as *mut u32).write_volatile(v);
}

#[inline(always)]
unsafe fn getreg32(r: u32) -> u32 {
(r as *mut u32).read_volatile()
}

#[allow(unused)]
pub(crate) fn wifi_reset_mac() {
const SYSCON_WIFI_RST_EN_REG: *mut u32 = (0x3ff00000 + 0xD0) as *mut u32;
const SYSTEM_MAC_RST: u32 = 1 << 2;

unsafe {
SYSCON_WIFI_RST_EN_REG
.write_volatile(SYSCON_WIFI_RST_EN_REG.read_volatile() | SYSTEM_MAC_RST);
SYSCON_WIFI_RST_EN_REG
.write_volatile(SYSCON_WIFI_RST_EN_REG.read_volatile() & !SYSTEM_MAC_RST);
}
}

/****************************************************************************
* Name: esp_dport_access_reg_read
*
Expand Down
43 changes: 9 additions & 34 deletions esp-wifi/src/common_adapter/common_adapter_esp32c2.rs
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,9 @@
use super::phy_init_data::PHY_INIT_DATA_DEFAULT;
use crate::binary::include::*;
use crate::common_adapter::RADIO_CLOCKS;
use crate::compat::common::StrBuf;
use crate::hal::system::RadioClockController;
use crate::hal::system::RadioPeripherals;
use atomic_polyfill::AtomicU32;
use log::trace;

Expand Down Expand Up @@ -111,10 +114,8 @@ fn phy_digital_regs_store() {

pub(crate) unsafe fn phy_enable_clock() {
trace!("phy_enable_clock");
const SYSTEM_WIFI_CLK_EN_REG: u32 = 0x60026000 + 0x014;
critical_section::with(|_| {
(SYSTEM_WIFI_CLK_EN_REG as *mut u32)
.write_volatile((SYSTEM_WIFI_CLK_EN_REG as *mut u32).read_volatile() | 0x78078F);
RADIO_CLOCKS.as_mut().unwrap().enable(RadioPeripherals::Phy);
});

trace!("phy_enable_clock done!");
Expand All @@ -123,40 +124,14 @@ pub(crate) unsafe fn phy_enable_clock() {
#[allow(unused)]
pub(crate) unsafe fn phy_disable_clock() {
trace!("phy_disable_clock");
const SYSTEM_WIFI_CLK_EN_REG: u32 = 0x60026000 + 0x014;
critical_section::with(|_| {
(SYSTEM_WIFI_CLK_EN_REG as *mut u32)
.write_volatile((SYSTEM_WIFI_CLK_EN_REG as *mut u32).read_volatile() & !0x78078F);
RADIO_CLOCKS
.as_mut()
.unwrap()
.disable(RadioPeripherals::Phy);
});

trace!("phy_enable_clock done!");
}

pub(crate) fn init_clocks() {
unsafe {
// PERIP_CLK_EN0
((0x600c0000 + 0x10) as *mut u32).write_volatile(0xffffffff);
// PERIP_CLK_EN1
((0x600c0000 + 0x14) as *mut u32).write_volatile(0xffffffff);
}

// APB_CTRL_WIFI_CLK_EN_REG
unsafe {
((0x60026000 + 0x14) as *mut u32).write_volatile(0xffffffff);
}
}

#[allow(unused)]
pub(crate) fn wifi_reset_mac() {
const SYSCON_WIFI_RST_EN_REG: *mut u32 = (0x60026000 + 0x18) as *mut u32;
const SYSTEM_MAC_RST: u32 = 1 << 2;

unsafe {
SYSCON_WIFI_RST_EN_REG
.write_volatile(SYSCON_WIFI_RST_EN_REG.read_volatile() | SYSTEM_MAC_RST);
SYSCON_WIFI_RST_EN_REG
.write_volatile(SYSCON_WIFI_RST_EN_REG.read_volatile() & !SYSTEM_MAC_RST);
}
trace!("phy_disable_clock done!");
}

#[no_mangle]
Expand Down
41 changes: 8 additions & 33 deletions esp-wifi/src/common_adapter/common_adapter_esp32c3.rs
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,9 @@
use super::phy_init_data::PHY_INIT_DATA_DEFAULT;
use crate::binary::include::*;
use crate::common_adapter::RADIO_CLOCKS;
use crate::compat::common::StrBuf;
use crate::hal::system::RadioClockController;
use crate::hal::system::RadioPeripherals;
use atomic_polyfill::AtomicU32;
use log::trace;

Expand Down Expand Up @@ -111,12 +114,9 @@ fn phy_digital_regs_store() {

pub(crate) unsafe fn phy_enable_clock() {
trace!("phy_enable_clock");
const SYSTEM_WIFI_CLK_EN_REG: u32 = 0x60026000 + 0x014;
critical_section::with(|_| {
(SYSTEM_WIFI_CLK_EN_REG as *mut u32)
.write_volatile((SYSTEM_WIFI_CLK_EN_REG as *mut u32).read_volatile() | 0x78078F);
RADIO_CLOCKS.as_mut().unwrap().enable(RadioPeripherals::Phy);
});

trace!("phy_enable_clock done!");
}

Expand All @@ -125,36 +125,11 @@ pub(crate) unsafe fn phy_disable_clock() {
trace!("phy_disable_clock");
const SYSTEM_WIFI_CLK_EN_REG: u32 = 0x60026000 + 0x014;
critical_section::with(|_| {
(SYSTEM_WIFI_CLK_EN_REG as *mut u32)
.write_volatile((SYSTEM_WIFI_CLK_EN_REG as *mut u32).read_volatile() & !0x78078F);
RADIO_CLOCKS
.as_mut()
.unwrap()
.disable(RadioPeripherals::Phy);
});

trace!("phy_enable_clock done!");
}

pub(crate) fn init_clocks() {
unsafe {
// PERIP_CLK_EN0
((0x600c0000 + 0x10) as *mut u32).write_volatile(0xffffffff);
// PERIP_CLK_EN1
((0x600c0000 + 0x14) as *mut u32).write_volatile(0xffffffff);
}

// APB_CTRL_WIFI_CLK_EN_REG
unsafe {
((0x60026000 + 0x14) as *mut u32).write_volatile(0xffffffff);
}
}

#[allow(unused)]
pub(crate) fn wifi_reset_mac() {
const SYSCON_WIFI_RST_EN_REG: *mut u32 = (0x60026000 + 0x18) as *mut u32;
const SYSTEM_MAC_RST: u32 = 1 << 2;

unsafe {
SYSCON_WIFI_RST_EN_REG
.write_volatile(SYSCON_WIFI_RST_EN_REG.read_volatile() | SYSTEM_MAC_RST);
SYSCON_WIFI_RST_EN_REG
.write_volatile(SYSCON_WIFI_RST_EN_REG.read_volatile() & !SYSTEM_MAC_RST);
}
}
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