catv-riscv

Simple single stage core that demonstrates the RV32 I instruction set. A "hello world" is provided that shows how to compile and link newlib (small libc) on such a minimal system.

Run with verilator

1. Enter the tb directory.
2. Compile the sample hello world by calling make all.
3. Compile the design by calling make verilate.
4. (Alternative) Compile design by calling make verilate VERI_FLAGS=--trace to produce a vcd dump in tb/logs when simulating.
5. Run the simulation with make run.

Run with QuestaSim

1. Enter the tb directory.
2. Compile the sample hello world by calling make all.
3. Compile and run the simulation with ./compile.sh && ./run.sh