Fix aarch64 load trap info: HeapOutOfBounds, not OutOfBounds. #1571
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This halfway solves a test failure: when temporarily disabling another assert that is triggered by lack of debug info, this causes the `custom_trap_handler` test to pass.
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cfallin
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This change adds SourceLoc information per instruction in a `VCode<Inst>` container, and keeps this information up-to-date across register allocation and branch reordering. The information is initially collected during instruction lowering, eventually collected on the MachSection, and finally provided to the environment that wraps the codegen crate for wasmtime. This PR is based on top of bytecodealliance#1570 and bytecodealliance#1571 (part of a series fixing tests). This PR depends on wasmtime/regalloc.rs#50, a change to the register allocator to provide instruction-granularity info on the rewritten instruction stream (rather than block-granularity). With the prior PRs applied as well, quite a few more unit tests pass; the exclusion list in bytecodealliance#1526 should be updated if this PR lands first.
bnjbvr
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Makes sense, thanks! I was thinking that setting the trap at so low a layer was a bad use of abstractions, and it might actually make sense to pass the TrapCode along the SourceLoc, up above during lowering. It is a preexisting issue, though, since 1. i implemented it this way, and 2. the x86 backend does the same thing as we do here (it uses this trap code in emit functions). So either way is fine.
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Agreed, we could clean up the way that traps are specified at some point -- something like "trap code to raise if this CLIF instruction fails for any one of a predetermined set of failure modes" (e.g., load/store to bad address, FP range/conversion/div-by-0, etc.) For now this fixes the test failures, though, so I'll go ahead and merge this! |
cfallin
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Apr 23, 2020
This change adds SourceLoc information per instruction in a `VCode<Inst>` container, and keeps this information up-to-date across register allocation and branch reordering. The information is initially collected during instruction lowering, eventually collected on the MachSection, and finally provided to the environment that wraps the codegen crate for wasmtime. This PR is based on top of bytecodealliance#1570 and bytecodealliance#1571 (part of a series fixing tests). This PR depends on wasmtime/regalloc.rs#50, a change to the register allocator to provide instruction-granularity info on the rewritten instruction stream (rather than block-granularity). With the prior PRs applied as well, quite a few more unit tests pass; the exclusion list in bytecodealliance#1526 should be updated if this PR lands first.
cfallin
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Apr 24, 2020
This change adds SourceLoc information per instruction in a `VCode<Inst>` container, and keeps this information up-to-date across register allocation and branch reordering. The information is initially collected during instruction lowering, eventually collected on the MachSection, and finally provided to the environment that wraps the codegen crate for wasmtime. This PR is based on top of bytecodealliance#1570 and bytecodealliance#1571 (part of a series fixing tests). This PR depends on wasmtime/regalloc.rs#50, a change to the register allocator to provide instruction-granularity info on the rewritten instruction stream (rather than block-granularity). With the prior PRs applied as well, quite a few more unit tests pass; the exclusion list in bytecodealliance#1526 should be updated if this PR lands first.
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This halfway solves a test failure: when temporarily disabling another
assert that is triggered by lack of debug info, this causes the
custom_trap_handlertest to pass.Validated that the
HeapOutOfBoundstrapcode is passed to theTrapSinkby the x86 backend's lowering of memory accesses as well.