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1. Systolic_Array_FPGA Systolic_Array_FPGA Public

   FPGA implementation of a systolic array for accelerated matrix multiplication.

   VHDL

2. Systolic_Array_UVM Systolic_Array_UVM Public

   UVM testbench for my 3x3 matrix multiplier design

   SystemVerilog

3. MAC_2_Stage MAC_2_Stage Public

   2-stage Multiply Accumulate (MAC) unit with UVM testbench

   SystemVerilog