Fiction is art and art is the triumph over chaos

.gitattributes

@@ -4,3 +4,4 @@ benchmarks/ISCAS89/* linguist-vendored
 benchmarks/EPFL/* linguist-vendored
 benchmarks/ITC99/* linguist-vendored
 *.v linguist-detectable=false
+*.fs linguist-detectable=false

CHANGELOG.md

@@ -3,6 +3,36 @@ All notable changes to this project will be documented in this file.
 
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/).
 
+## v0.2.1 - 2019-05-02
+*Fiction is art and art is the triumph over chaos.* — John Cheever
+
+### Added
+- Support for BANCS clocking and integration in `exact`
+- Name strings for `fcn_clocking_scheme` objects and corresponding name-based look-up
+- Version and build information accessible within the code by including `version.h`
+- Parameter `-i` for command `ortho`
+- `shortcuts.fs` with predefined flows
+- `benchmarks/MAJ/` folder with some TOY benchmarks using MAJ gates
+
+### Changed
+- Calls to `exact -s` now need to name the desired clocking, e.g. `exact -s use` (case insensitive)
+- `incoming`/`outgoing_information_flow_tiles` have been renamed to `incoming`/`outgoing_data_flow` and handle multi wires now
+- Renamed diagonal clocking schemes to 2DDWAVE and gave proper credit.
+- More verbose error messages
+
+### Fixed
+- TP calculation for layouts without designated I/O pins (thanks to Mario Kneidinger!)
+- I/O port orientation of PI/PO gates using QCA-ONE library
+- Usage of non-PI/PO MAJ gates in QCA-ONE library
+- Visualization of clock latches in `show -c` (thanks to Gregor Kuhn!)
+- Multi direction assignment to wires and gates in `exact` leading to physically impossible layouts
+- `shrink_to_fit` in `fcn_gate_layout` incorporates the BGL bug now. Minimum size in each dimension is 2.
+For more information, see <https://svn.boost.org/trac10/ticket/11735>
+- Parameters for `exact` no longer get stuck once set
+
+### Removed
+- Parameter `-n` for `exact`
+
 ## v0.2.0 - 2019-03-21
 *Fiction reveals the truth that reality obscures.* &mdash; Jessamyn West
 ### Added
@@ -22,8 +52,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/).
 - `write_qca` is now called `qca` and handles file names automatically if necessary
 - `-u` is not a required parameter for `exact` anymore
 - Richer output for `print -w`
-- Included latest bugfixes for [Alice](https://github.com/msoeken/alice)
-- Included latest update for [Lorina](https://github.com/hriener/lorina)
+- Included latest bugfixes for [alice](https://github.com/msoeken/alice)
+- Included latest update for [lorina](https://github.com/hriener/lorina)
 
 ### Fixed
 - Starting layout size for calls to `exact -i` was too low and has been corrected

CMakeLists.txt

@@ -1,7 +1,7 @@
 cmake_minimum_required(VERSION 3.2)
 project(fiction
         LANGUAGES CXX
-        VERSION 0.2.0)
+        VERSION 0.2.1)
 
 # C++14
 set(CMAKE_CXX_STANDARD 14)
@@ -22,6 +22,10 @@ include_directories(src/algo/ src/io/ src/tech/ src/topo/ src/util/)
 
 # Find source files
 file(GLOB_RECURSE SOURCES src/*.cpp src/*.h)
+# Add configuration file
+configure_file(src/util/version.h.in util/version.h)
+# Include configuration file
+include_directories(${PROJECT_BINARY_DIR}/util/)
 
 # Require Boost libraries
 find_package(Boost COMPONENTS system filesystem REQUIRED)
@@ -30,7 +34,7 @@ if(Boost_FOUND)
     link_directories(${Boost_LIBRARY_DIRS})
 endif()
 
-# custom install prefix for libraries
+# Custom install prefix for libraries
 set(LIB_PREFIX ${CMAKE_SOURCE_DIR}/libs)
 
 # Clone, build and locally install Z3
@@ -49,21 +53,21 @@ ExternalProject_Add(z3
         LOG_INSTALL       1
         LOG_BUILD         1)
 
-# include Z3
+# Include Z3
 include_directories(${Z3_DIR}/include/)
 
-# include cppitertools
+# Include cppitertools
 include_directories(${LIB_PREFIX}/cppitertools/)
 
-# include alice
+# Include alice
 add_subdirectory(${LIB_PREFIX}/alice/)
 
-# include lorina
+# Include lorina
 add_subdirectory(${LIB_PREFIX}/lorina/)
 
-# build executable
+# Build executable
 add_executable(fiction ${SOURCES})
 add_dependencies(fiction z3)
 
-# link against Boost, Z3, alice, and lorina
+# Link against Boost, Z3, alice, and lorina
 target_link_libraries(fiction ${Boost_LIBRARIES} ${Z3_DIR}/lib/libz3.so alice lorina)

README.md

@@ -25,11 +25,11 @@ More technologies and libraries are to come!
 An [exact approach](http://www.informatik.uni-bremen.de/agra/doc/konf/2018DATE_ExactMethodforDesignExplorationOfQCA.pdf)
 in terms of circuit area is provided which is the first one ever in the field of FCN circuits.
 It is based on Satisfiability Modulo Theories (SMT) and utilizes the solver engine [Z3](https://github.com/Z3Prover/z3)
-by Microsoft Research. It is only feasable for small circuits but provides the best results.
+by Microsoft Research. It is only feasible for small circuits but provides the best results.
 
 Additionally, a [scalable method](http://www.informatik.uni-bremen.de/agra/doc/konf/2019_ASP-DAC_Scalable_Design_for_Field-coupled_Nanocomputing_Circuits.pdf)
 is implemented which is based on Orthogonal Graph Drawing (OGD). It has a huge runtime advantage compared to the SMT technique.
-Though, its results are not optimal in terms of area. It is feasable even for larger circuits and provides results real quick.
+Though, its results are not optimal in terms of area. It is feasible even for larger circuits and provides results real quick.
 
 This is ongoing research but more algorithms are to come!
 
@@ -49,7 +49,7 @@ CMake will inform you about missing dependencies during the build process.
 Check out the git project (and all of its submodules) using the following command:
 
 ```sh
-git clone https://github.com/marcelwa/fiction.git --recursive
+git clone https://gitlab.informatik.uni-bremen.de/m_walter/fiction.git --recursive
 ```
 
 Several third-party libraries will be cloned within the `libs/` folder. The `cmake` build process will take care of
@@ -150,7 +150,7 @@ parse all parsable files within that given directory powered by the [lorina](htt
 by Heinz Riener. The flag `-s` allows prior sorting. The content of the logic network store can be briefly viewed by
 entering `store -w` whereas `print -w` writes a [Graphviz](https://www.graphviz.org/) dot file of the current network
 to the standard output. Arbitrarily many logic networks can be held in store from which the latest is always the
-active one. Change active network with `set -w <n>` where you replace `<n>` by the number of the store element you
+active one. Change active network with `current -w <n>` where you replace `<n>` by the number of the store element you
 want to activate.
 
 ### Placement & Routing
@@ -163,19 +163,19 @@ and route the current network on 25 FCN tiles, utilizing crossings (`-x`) and ar
 balancing I/O paths to internally synchronize the circuit using designated pins (`-i`) plus routing all I/Os to the
 grid borders for easier access (`-b`).
 
-Additionally, you can provide a pre-defined clocking scheme to prune the search space. Doing so by option `-s` expects a
-number where `0` represents default open clocking, `1` is
-[USE](https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7219390), `2` is a simple diagonal scheme, and `3` is the
-[RES](https://www.tandfonline.com/doi/pdf/10.1080/21681724.2019.1570551?needAccess=true) clocking. Additionally,
-a number of clock phases to use can be specified by utilizing the `-n` flag. Currently, only 3- and 4-phase clockings
-are supported. Additional clocking schemes can be implemented in the header file `fcn_clocking_scheme.h`.
+Additionally, you can provide a pre-defined clocking scheme to prune the search space with option `-s`. Possible schemes
+besides the default open clocking, are [2DDWave](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1717097),
+[USE](https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7219390),
+[RES](https://www.tandfonline.com/doi/pdf/10.1080/21681724.2019.1570551?needAccess=true), and
+[BANCS](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8533251&tag=1). For detailed information on usage see
+`exact -h`. Additional clocking schemes can be implemented in the header file `fcn_clocking_scheme.h`.
 
 Calls to `ortho` are not expecting flags. This algorithm based on orthogonal graph drawing produces layouts in much
 shorter time. Though their quality in terms of area is far from optimum. Plus, for physical implementation, it might be
 necessary to route primary inputs/outputs to the grid borders by hand.
 
 Generated FCN gate layouts are also saved in stores. Entering `store -g` shows a list of all gate layouts available.
-Statistical informations about store elements can be printed using command `ps`. For a gate layout, a call to `ps -g`
+Statistical information about store elements can be printed using command `ps`. For a gate layout, a call to `ps -g`
 could for instance output the following.
 ```
 c17 - 5 × 7, #G: 18, #W: 18, #C: 3, #L: 0, CP: 11, TP: 1/1
@@ -205,7 +205,7 @@ in store. If you want to just generate the SVG file without opening it in your s
 Alternatively, open the exported file with a different program by using `show -c --program "\"google-chrome\" {}"` for
 instance to open it with your Chrome browser. Note, that this behavior is platform dependent and might not work properly
 under your system. For more information see `show --help` or the full
-[Alice documentation](https://libalice.readthedocs.io/en/latest/index.html).
+[alice documentation](https://libalice.readthedocs.io/en/latest/index.html).
 
 The used color scheme is based on the one known from [QCADesigner](https://waluslab.ece.ubc.ca/qcadesigner/).
 
@@ -232,8 +232,12 @@ which can be executed by `./fiction -ef c17_synth.fs -l c17_log.json` where stat
 called `c17_log.json`.
 
 These scripts can also be nested. Use `< script.fs` within a *fiction script* to load `script.fs` in that very position.
+A script called `shortcuts.fs` has been placed in the top level folder. It can be loaded on start-up by calling
+`./fiction -if ../shortcuts.fs` in the build folder. This makes predefined commands and flows available as shortcuts.
+Try `synth xibs use` for instance to perform the whole flow of layouting (utilizing `USE` clocking) and physical
+synthesis down to cell level including visual representation.
 
-Additionally, *fiction* can also be part of a bash script. Consider the following snippet
+Additionally, *fiction* itself can be part of a bash script. Consider the following snippet
 
 ```sh
 for filepath in ../benchmarks/TOY/*.v; do

benchmarks/MAJ/1bitAdderAOIG.v

@@ -0,0 +1,14 @@
+module top(x0, x1, x2, y0, y1);
+  input x0, x1, x2;
+  output y0, y1;
+  wire n4, n5, n6, n7, n8, n9, n10;
+  assign n4 = x1 & x2;
+  assign n5 = (x1 & x2) | (x1 & ~n4) | (x2 & ~n4);
+  assign n6 = ~n4 & n5;
+  assign n7 = x0 & n6;
+  assign n8 = x0 | n6;
+  assign n9 = ~n7 & n8;
+  assign n10 = n4 | n7;
+  assign y0 = n9;
+  assign y1 = n10;
+endmodule

benchmarks/MAJ/1bitAdderMaj.v

@@ -0,0 +1,7 @@
+module top(x0, x1, x2, y0);
+  input x0, x1, x2;
+  output y0;
+  wire n4;
+  assign n4 = (x0 & x1) | (x0 & ~x2) | (x1 & ~x2);
+  assign y0 = n4;
+endmodule

benchmarks/MAJ/RCA2.v

@@ -0,0 +1,19 @@
+module top(x0, x1, x2, x3, x4, y0, y1, y2);
+  input x0, x1, x2, x3, x4;
+  output y0, y1, y2;
+  wire n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16;
+  assign n6 = x0 | x2;
+  assign n7 = (x0 & x2) | (x0 & ~n6) | (x2 & ~n6);
+  assign n8 = n6 & ~n7;
+  assign n9 = x4 & n8;
+  assign n10 = (x4 & n8) | (x4 & ~n9) | (n8 & ~n9);
+  assign n11 = ~n9 & n10;
+  assign n12 = x1 & n9;
+  assign n13 = x1 & x3;
+  assign n14 = (~x1 & n9) | (~x1 & n13) | (n9 & n13);
+  assign n15 = (x1 & ~n12) | (x1 & n14) | (~n12 & n14);
+  assign n16 = (x1 & x4) | (x1 & n13) | (x4 & n13);
+  assign y0 = n11;
+  assign y1 = n15;
+  assign y2 = n16;
+endmodule

benchmarks/MAJ/clpl.v

@@ -0,0 +1,20 @@
+module top(x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, y0, y1, y2, y3, y4);
+  input x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10;
+  output y0, y1, y2, y3, y4;
+  wire n12, n13, n14, n15, n16, n17, n18, n19, n20, n21;
+  assign n12 = x1 | x6;
+  assign n13 = x0 & x4;
+  assign n14 = x2 | n13;
+  assign n15 = x3 | x5;
+  assign n16 = (x3 & n14) | (x3 & n15) | (n14 & n15);
+  assign n17 = (x1 & n12) | (x1 & n16) | (n12 & n16);
+  assign n18 = x9 | x10;
+  assign n19 = x7 | x8;
+  assign n20 = (x7 & n17) | (x7 & n19) | (n17 & n19);
+  assign n21 = (x10 & n18) | (x10 & n20) | (n18 & n20);
+  assign y0 = n17;
+  assign y1 = n16;
+  assign y2 = n14;
+  assign y3 = n21;
+  assign y4 = n20;
+endmodule

benchmarks/MAJ/mux21.v

@@ -0,0 +1,9 @@
+module top(x0, x1, x2, y0);
+  input x0, x1, x2;
+  output y0;
+  wire n4, n5, n6;
+  assign n4 = x0 | x2;
+  assign n5 = ~x1 & x2;
+  assign n6 = n4 & ~n5;
+  assign y0 = n6;
+endmodule

benchmarks/MAJ/mux41.v

@@ -0,0 +1,13 @@
+module top(x0, x1, x2, x3, x4, x5, y0);
+  input x0, x1, x2, x3, x4, x5;
+  output y0;
+  wire n7, n8, n9, n10, n11, n12, n13;
+  assign n7 = (x0 & x4) | (x0 & ~x5) | (x4 & ~x5);
+  assign n8 = (~x1 & x4) | (~x1 & x5) | (x4 & x5);
+  assign n9 = n7 & ~n8;
+  assign n10 = (x3 & ~x4) | (x3 & x5) | (~x4 & x5);
+  assign n11 = (x2 & x4) | (x2 & x5) | (x4 & x5);
+  assign n12 = n10 & ~n11;
+  assign n13 = (n9 & n10) | (n9 & ~n12) | (n10 & ~n12);
+  assign y0 = n13;
+endmodule

benchmarks/MAJ/newtag.v

@@ -0,0 +1,12 @@
+module top(x0, x1, x2, x3, x4, x5, x6, x7, y0);
+  input x0, x1, x2, x3, x4, x5, x6, x7;
+  output y0;
+  wire n9, n10, n11, n12, n13, n14;
+  assign n9 = (~x3 & x6) | (~x3 & x7) | (x6 & x7);
+  assign n10 = (x4 & x5) | (x4 & n9) | (x5 & n9);
+  assign n11 = x3 & ~n10;
+  assign n12 = x1 & ~x2;
+  assign n13 = ~x0 & n12;
+  assign n14 = ~n11 & n13;
+  assign y0 = ~n14;
+endmodule

benchmarks/MAJ/par_check.v

@@ -0,0 +1,11 @@
+module top(x0, x1, x2, x3, y0);
+  input x0, x1, x2, x3;
+  output y0;
+  wire n5, n6, n7, n8, n9;
+  assign n5 = (x0 & x1) | (x0 & ~x2) | (x1 & ~x2);
+  assign n6 = x3 | n5;
+  assign n7 = (~x0 & x2) | (~x0 & n5) | (x2 & n5);
+  assign n8 = ~x3 & n7;
+  assign n9 = (~x1 & n6) | (~x1 & n8) | (n6 & n8);
+  assign y0 = n9;
+endmodule

benchmarks/MAJ/par_gen.v

@@ -0,0 +1,9 @@
+module top(x0, x1, x2, y0);
+  input x0, x1, x2;
+  output y0;
+  wire n4, n5, n6;
+  assign n4 = (~x0 & x1) | (~x0 & x2) | (x1 & x2);
+  assign n5 = (x1 & x2) | (x1 & ~n4) | (x2 & ~n4);
+  assign n6 = (x0 & n4) | (x0 & ~n5) | (n4 & ~n5);
+  assign y0 = n6;
+endmodule

benchmarks/MAJ/t.v

@@ -0,0 +1,12 @@
+module top(x0, x1, x2, x3, x4, y0, y1);
+  input x0, x1, x2, x3, x4;
+  output y0, y1;
+  wire n6, n7, n8, n9, n10;
+  assign n6 = x2 & x3;
+  assign n7 = x1 & ~n6;
+  assign n8 = x0 & x2;
+  assign n9 = n7 | n8;
+  assign n10 = (x4 & ~n6) | (x4 & n7) | (~n6 & n7);
+  assign y0 = n9;
+  assign y1 = n10;
+endmodule

benchmarks/MAJ/xnor2.v

@@ -0,0 +1,9 @@
+module top(x0, x1, y0);
+  input x0, x1;
+  output y0;
+  wire n3, n4, n5;
+  assign n3 = x0 | x1;
+  assign n4 = (x0 & x1) | (x0 & ~n3) | (x1 & ~n3);
+  assign n5 = n3 & ~n4;
+  assign y0 = ~n5;
+endmodule

benchmarks/MAJ/xor2.v

@@ -0,0 +1,9 @@
+module top(x0, x1, y0);
+  input x0, x1;
+  output y0;
+  wire n3, n4, n5;
+  assign n3 = x0 | x1;
+  assign n4 = (x0 & x1) | (x0 & ~n3) | (x1 & ~n3);
+  assign n5 = n3 & ~n4;
+  assign y0 = n5;
+endmodule

benchmarks/MAJ/xor5R.v

@@ -0,0 +1,12 @@
+module top(x0, x1, x2, x3, x4, y0);
+  input x0, x1, x2, x3, x4;
+  output y0;
+  wire n6, n7, n8, n9, n10, n11;
+  assign n6 = (~x0 & x1) | (~x0 & x2) | (x1 & x2);
+  assign n7 = (x1 & x2) | (x1 & ~n6) | (x2 & ~n6);
+  assign n8 = (x0 & n6) | (x0 & ~n7) | (n6 & ~n7);
+  assign n9 = (~x3 & x4) | (~x3 & n8) | (x4 & n8);
+  assign n10 = (x4 & n8) | (x4 & ~n9) | (n8 & ~n9);
+  assign n11 = (x3 & n9) | (x3 & ~n10) | (n9 & ~n10);
+  assign y0 = n11;
+endmodule

benchmarks/MAJ/xor5_r1.v

@@ -0,0 +1,12 @@
+module top(x0, x1, x2, x3, x4, y0);
+  input x0, x1, x2, x3, x4;
+  output y0;
+  wire n6, n7, n8, n9, n10, n11;
+  assign n6 = (~x0 & x1) | (~x0 & x2) | (x1 & x2);
+  assign n7 = (x1 & x2) | (x1 & ~n6) | (x2 & ~n6);
+  assign n8 = (x0 & n6) | (x0 & ~n7) | (n6 & ~n7);
+  assign n9 = (~x3 & x4) | (~x3 & n8) | (x4 & n8);
+  assign n10 = (x4 & n8) | (x4 & ~n9) | (n8 & ~n9);
+  assign n11 = (x3 & n9) | (x3 & ~n10) | (n9 & ~n10);
+  assign y0 = n11;
+endmodule

shortcuts.fs

@@ -0,0 +1,10 @@
+# commands
+alias "xibs(.*)" "exact -x -i -b -s{}"
+
+# flows
+alias "synth(.*)" "{}; cell; show"
+alias "phys(.*)" "{}; cell; qca"
+
+# load
+alias "mux" "read ../benchmarks/TOY/mux21.v"
+alias "rca" "read ../benchmarks/TOY/RCA2.v"