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✨ Compile time flows and CLI simulation update (#349)
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* ✨ Added CMake options for select flow compilation

* 🎨 Simplified layout printing from store

* ✨ Added SQD reading and CDS printing to the CLI

* ✨ Added QuickExact to the CLI

* ✨ Added QuickSim to the CLI

* 🐛 Try to pacify MSVC

* 🐛 Removed base option for the quicksim CLI command

* 🎨 Adjusted `minimum_energy` to be more C++-ish

* ✨ Added a `minimum_energy_distribution` function to obtain the CDS with minimum energy from a range

* 📝 Fixed a wrong header in the documentation and added a missing `:members:` statement

* 🎨 Make the quicksim and quickexact commands pick the minimum energy state they found

* 🐛 Fixed cyclic dependency

* 💥 Made `additional_simulation_parameters` in `sidb_simulation_result` an `std::unordered_map`

* ✨ Made the quicksim CLI command log its additional parameters

* ✨ Display proper cell type names in the CLI's `ps -c` and `store -c` commands

* ✅ update unit tests after code changes.

* ✅ update test after code changes.

* 🎨 remove ``else`` after return.

* 🎨 ClangFormat changes

Signed-off-by: ClangFormat <[email protected]>

* 📝 Add documentation to the CLI chapter in the RTD pages.

* 📝 revert wrong changes.

* 🎨 three as a base number is not supported by quicksim.

* 📝 change position of simulation paragraph.

* ✅ update test due to code changes.

* 💚 try to fix macos issue.

* 🎨 add global potential and automatic base number detection.

* 📝 Extended documentation on `minimum_energy` to reflect the error cases

* 🐛 Fixed unit

* 📝 Small doc update

* 📝 Revert Jan's change

* :bug Add missing header

* 🎨 delete automatic base number detection.

* 🐛 Set CMP0135 only if CMake >= 3.24 is used

* 🎨 disable automatic base number detection in CLI.

* 📝 add variable names.

* 🎨 Cleaned up includes

* 🔥 Remove base toggle from quickexact and quicksim CLI commands

* 🎨 Further header include fixes

* 🎨 Adjustments to logging and [[nodiscard]]

* ✨ Added Operational Domain computation to the CLI

* ✨ Added Operational Domain computation to the CLI

* 📝 Added Operational Domain CLI documentation

* 🐛 Added missing includes to `critical_temperature`

* 📝 Small doc fix

* 🐛 Added missing includes to `quicksim`

* 🐛 Added missing includes to `quicksim`'s tests

* 🎨 Code cleanup in `critical_temperature`

* 🎨 Added physical parameters used for the simulation to the `critical_temperature_stats`

* 🐛 Fix logging for `quickexact` and `quicksim` CLI commands

* 🐛 Fix `opdom` error when no PI/PO cells are available

* ✨ Added command `temp` for critical temperature SiDB simulation to the CLI

* 🎨 Added missing header and `std::forward`

* 🐛 fix unit bug.

* 🎨 set description to meV.

---------

Signed-off-by: ClangFormat <[email protected]>
Co-authored-by: Drewniok <[email protected]>
Co-authored-by: ClangFormat <[email protected]>
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@marcelwa @Drewniok
3 people committed Dec 15, 2023
1 parent 1764242 commit 2e3446c
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Showing 33 changed files with 1,567 additions and 284 deletions.
20 changes: 20 additions & 0 deletions cli/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,26 @@ add_executable(fiction ${SOURCES})
# Link against the project settings, libfiction and alice
target_link_libraries(fiction PRIVATE libfiction alice)

# Compile-time decisions on which flows to compile

# Logic synthesis flow
option(FICTION_LOGIC_SYNTHESIS_FLOW "Enable the logic synthesis flow for the fiction CLI" ON)
if(FICTION_LOGIC_SYNTHESIS_FLOW)
target_compile_definitions(fiction PRIVATE FICTION_LOGIC_SYNTHESIS_FLOW)
endif()

# Physical design flow
option(FICTION_PHYSICAL_DESIGN_FLOW "Enable the physical design flow for the fiction CLI" ON)
if(FICTION_PHYSICAL_DESIGN_FLOW)
target_compile_definitions(fiction PRIVATE FICTION_PHYSICAL_DESIGN_FLOW)
endif()

# Physical simulation flow
option(FICTION_SIMULATION_FLOW "Enable the physical simulation flow for the fiction CLI" ON)
if(FICTION_SIMULATION_FLOW)
target_compile_definitions(fiction PRIVATE FICTION_SIMULATION_FLOW)
endif()

# Strip the executable if we are in Release mode
if(CMAKE_BUILD_TYPE STREQUAL "Release")
if(CMAKE_STRIP)
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72 changes: 46 additions & 26 deletions cli/cmd/io/read.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@
#include <fiction/io/network_reader.hpp>
#include <fiction/io/read_fgl_layout.hpp>
#include <fiction/io/read_fqca_layout.hpp>
#include <fiction/io/read_sqd_layout.hpp>
#include <fiction/types.hpp>

#include <alice/alice.hpp>
Expand All @@ -23,9 +24,9 @@ namespace alice
*
* Currently parses Verilog, AIGER, and BLIF using the lorina parsers.
*
* Parses FGL and FQCA via custom reader functions.
*
* For more information see: https://github.com/hriener/lorina
*
* Parses FGL, SQD, and FQCA via custom reader functions.
*/
class read_command : public command
{
Expand All @@ -40,54 +41,57 @@ class read_command : public command
"which will be put into the respective store. Current supported file types are:\n"
"Logic networks: Verilog, AIGER, BLIF.\n"
"Gate-level layouts: FGL.\n"
"Cell-level layouts: FQCA.\n"
"Cell-level layouts: SQD, FQCA.\n"
"In a directory, only files with extension '.v', '.aig', '.blif' are considered.")
{
add_option("filename", filename, "Filename or directory")->required();
add_option("topology", topology,
"Topology for gate-level layouts. Can be 'cartesian' or of the form "
"'<odd|even>_<row|column>_<cartesian|hex>'");
add_flag("--aig,-a", "Parse file as AIG");
add_flag("--xag,-x", "Parse file as XAG");
add_flag("--mig,-m", "Parse file as MIG");
add_flag("--tec,-t", "Parse file as technology network");
add_flag("--fgl,-f", "Parse file as fiction gate-level layout");
add_flag("--qca,-q", "Parse file as QCA cell-level layout");
add_flag("--sort,-s", sort, "Sort networks in given directory by vertex count prior to storing them");
add_flag("--aig,-a", "Parse Verilog file as AIG");
add_flag("--xag,-x", "Parse Verilog file as XAG");
add_flag("--mig,-m", "Parse Verilog file as MIG");
add_flag("--tec,-t", "Parse Verilog file as technology network");
add_flag("--fgl,-f", "Parse FGL file as fiction gate-level layout");
add_flag("--sqd,-s", "Parse SQD file as SiDB cell-level layout");
add_flag("--fqca,-q", "Parse FQCA file as QCA cell-level layout");
add_flag("--sort", sort, "Sort networks in given directory by node count prior to storing them");
}

protected:
/**
* Function to perform the read call. Reads Verilog and creates a logic_network.
* Function to perform the read call. Reads a network or layout from a file.
*/
void execute() override
{
const auto store_ntks = [&](auto&& reader)
{
for (const auto& ln : reader.get_networks(sort))
{
store<fiction::logic_network_t>().extend() = ln;
}
};

if (!is_set("aig") && !is_set("xag") && !is_set("mig") && !is_set("tec") && !is_set("fgl") && !is_set("qca"))
if (!is_set("aig") && !is_set("xag") && !is_set("mig") && !is_set("tec") && !is_set("fgl") && !is_set("sqd") &&
!is_set("fqca"))
{
env->out() << "[e] at least one network or layout type must be specified" << std::endl;
}
else if ((is_set("aig") || is_set("xag") || is_set("mig") || is_set("tec")) && is_set("fql"))
else if ((is_set("aig") || is_set("xag") || is_set("mig") || is_set("tec")) && is_set("fgl"))
{
env->out() << "[e] cannot parse files as both logic networks and gate-level layouts" << std::endl;
}
else if ((is_set("aig") || is_set("xag") || is_set("mig") || is_set("tec")) && is_set("qca"))
else if ((is_set("aig") || is_set("xag") || is_set("mig") || is_set("tec")) &&
(is_set("sqd") || is_set("fqca")))
{
env->out() << "[e] cannot parse files as both logic networks and cell-level layouts" << std::endl;
}
else if (is_set("fql") && is_set("qca"))
else if (is_set("fgl") && (is_set("sqd") || is_set("fqca")))
{
env->out() << "[e] cannot parse files as both gate-level and cell-level layouts" << std::endl;
}
else
{
const auto store_ntks = [&](auto&& reader)
{
for (const auto& ln : reader.get_networks(sort))
{
store<fiction::logic_network_t>().extend() = ln;
}
};

try
{
if (is_set("aig"))
Expand All @@ -114,7 +118,7 @@ class read_command : public command

store_ntks(reader);
}
if (is_set("fgl") || is_set("qca"))
if (is_set("fgl") || is_set("sqd") || is_set("fqca"))
{
if (std::filesystem::exists(filename))
{
Expand Down Expand Up @@ -205,7 +209,23 @@ class read_command : public command
<< std::endl;
}
}
if (is_set("qca"))
else if (is_set("sqd"))
{
try
{
const auto layout_name = std::filesystem::path{filename}.stem().string();

store<fiction::cell_layout_t>().extend() =
std::make_shared<fiction::sidb_cell_clk_lyt>(
fiction::read_sqd_layout<fiction::sidb_cell_clk_lyt>(filename,
layout_name));
}
catch (const fiction::sqd_parsing_error& e)
{
env->out() << e.what() << std::endl;
}
}
else if (is_set("fqca"))
{
try
{
Expand Down Expand Up @@ -250,7 +270,7 @@ class read_command : public command
}
catch (...)
{
env->out() << "[e] no networks or layouts were read" << std::endl;
env->out() << "[e] I/O error: no file could be read" << std::endl;
}
}

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