SiDB Bestagon gate library (#32)

* exp: Updated the Bestagon experiments

* docs: Added RST documentation for the Bestagon gate library

README.md

@@ -94,7 +94,11 @@ File formats:
 
 Many thanks to Umberto Garlando and Fabrizio Riente for their support!
 
-### Silicon Dangling Bond (SiDB)
+### Silicon Dangling Bonds (SiDBs)
+
+Gate libraries:
+
+- [Bestagon](https://fiction.readthedocs.io/en/latest/technology/gate_libraries.html#sidb-bestagon-library)
 
 File formats:
 

docs/technology/gate_libraries.rst

@@ -48,3 +48,11 @@ iNML ToPoliNano Library
 .. doxygenclass:: fiction::inml_topolinano_library
    :members:
 
+
+SiDB Bestagon Library
+---------------------
+
+**Header:** ``fiction/technology/sidb_bestagon_library.hpp``
+
+.. doxygenclass:: fiction::sidb_bestagon_library
+   :members:

experiments/bestagon/bestagon.cpp

@@ -100,10 +100,9 @@ int main()
     exact_params.timeout       = 3'600'000;  // 1h in ms
     fiction::exact_physical_design_stats exact_stats{};
 
-    constexpr const uint64_t bench_select = fiction_experiments::all & ~fiction_experiments::parity &
-                                            ~fiction_experiments::xor5_maj & ~fiction_experiments::two_bit_add_maj &
-                                            ~fiction_experiments::cm82a_5 & ~fiction_experiments::xor5_r1 &
-                                            ~fiction_experiments::b1_r2 & ~fiction_experiments::clpl;
+    static constexpr const uint64_t bench_select = fiction_experiments::all & ~fiction_experiments::b1_r2 &
+                                                   ~fiction_experiments::clpl & ~fiction_experiments::two_bit_add_maj &
+                                                   ~fiction_experiments::parity;
 
     for (const auto& benchmark : fiction_experiments::all_benchmarks(bench_select))
     {

experiments/fiction_experiments.hpp

@@ -15,6 +15,7 @@
 
 namespace fiction_experiments
 {
+
 // clang-format off
 
 /* Trindade et al. 2016 benchmarks */
@@ -60,40 +61,43 @@ static const char* benchmarks[] = {
 
 std::vector<std::string> trindade16_benchmarks(uint64_t selection = trindade16)
 {
-    std::vector<std::string> result;
+    std::vector<std::string> result{};
     for (uint32_t i = 0u; i < 7u; ++i)
     {
         if ((selection >> i) & 1)
         {
             result.emplace_back(benchmarks[i]);
         }
     }
+
     return result;
 }
 
 std::vector<std::string> fontes18_benchmarks(uint64_t selection = fontes18)
 {
-    std::vector<std::string> result;
-    for (uint32_t i = 7u; i < 17u; ++i)
+    std::vector<std::string> result{};
+    for (uint32_t i = 7u; i < 23u; ++i)
     {
         if ((selection >> i) & 1)
         {
             result.emplace_back(benchmarks[i]);
         }
     }
+
     return result;
 }
 
 std::vector<std::string> all_benchmarks(uint64_t selection = all)
 {
-    std::vector<std::string> result;
-    for (uint32_t i = 0u; i < 17u; ++i)
+    std::vector<std::string> result{};
+    for (uint32_t i = 0u; i < 23u; ++i)
     {
         if ((selection >> i) & 1)
         {
             result.emplace_back(benchmarks[i]);
         }
     }
+
     return result;
 }
 

include/fiction/technology/inml_topolinano_library.hpp

@@ -31,14 +31,13 @@ class inml_topolinano_library : public fcn_gate_library<inml_technology, 4, 4>
   public:
     explicit inml_topolinano_library() = delete;
     /**
-     * Overrides the corresponding function in fcn_gate_library. Given a tile t, this function takes all
-     * necessary information from the stored grid into account to choose the correct fcn_gate representation for
-     * that tile. May it be a gate or wires. Rotation and special marks like input and output, const cells etc.
-     * are computed additionally.
+     * Given a tile t, this function takes all necessary information from the stored grid into account to choose the
+     * correct fcn_gate representation for that tile. May it be a gate or wires. Rotation and special marks like input
+     * and output, const cells etc. are computed additionally.
      *
      * @tparam GateLyt Gate-level layout type.
      * @param lyt Gate-level layout that hosts tile t.
-     * @param t Tile to be realized in the ToPoliNano library.
+     * @param t Tile to be realized as a ToPoliNano gate.
      * @return ToPoliNano gate representation of t including I/Os, rotation, etc.
      */
     template <typename GateLyt>

include/fiction/technology/qca_one_library.hpp

@@ -32,14 +32,13 @@ class qca_one_library : public fcn_gate_library<qca_technology, 5, 5>
   public:
     explicit qca_one_library() = delete;
     /**
-     * Overrides the corresponding function in fcn_gate_library. Given a tile t, this function takes all
-     * necessary information from the stored grid into account to choose the correct fcn_gate representation for
-     * that tile. May it be a gate or wires. Rotation and special marks like input and output, const cells etc.
-     * are computed additionally.
+     * Given a tile t, this function takes all necessary information from the stored grid into account to choose the
+     * correct fcn_gate representation for that tile. May it be a gate or wires. Rotation and special marks like input
+     * and output, const cells etc. are computed additionally.
      *
      * @tparam GateLyt Gate-level layout type.
      * @param lyt Gate-level layout that hosts tile t.
-     * @param t Tile to be realized in QCA ONE.
+     * @param t Tile to be realized as a QCA ONE gate.
      * @return QCA ONE gate representation of t including I/Os, rotation, const cells, etc.
      */
     template <typename GateLyt>

include/fiction/technology/sidb_bestagon_library.hpp

@@ -20,11 +20,30 @@
 namespace fiction
 {
 
+/**
+ * A gate library for the SiDB technology that is based on Y-shaped gates in hexagonal tiles. Y-shaped gates have been
+ * first introduced in "Binary Atomic Silicon Logic" by Taleana Huff, Hatem Labidi, Mohammad Rashidi, Lucian Livadaru,
+ * Thomas Dienel, Roshan Achal, Wyatt Vine, Jason Pitters, and Robert A. Wolkow in Nature Electronics 2018. The Bestagon
+ * library was later proposed in "Hexagons are the Bestagons: Design Automation for Silicon Dangling Bond Logic" by
+ * Marcel Walter, Samuel Sze Hang Ng, Konrad Walus, and Robert Wille in Design Automation Conference 2022. The goal of
+ * the Bestagon library is to be as close to physically realizable SiDB circuits as possible by taking fabrication
+ * limitations of, e.g., clocking electrodes into account while also relying on established gate shape. Thus, the
+ * hexagonal tiles in the Bestagon library are quite large with a lot of free space to avoid unwanted gate interactions.
+ */
 class sidb_bestagon_library : public fcn_gate_library<sidb_technology, 60, 46>  // width and height of a hexagon
 {
   public:
     sidb_bestagon_library() = delete;
-
+    /**
+     * Given a tile t, this function takes all necessary information from the stored grid into account to choose the
+     * correct fcn_gate representation for that tile. May it be a gate or wires. Rotation and special marks like input
+     * and output, const cells etc. are computed additionally.
+     *
+     * @tparam GateLyt Gate-level layout type.
+     * @param lyt Gate-level layout that hosts tile t.
+     * @param t Tile to be realized as a Bestagon gate.
+     * @return Bestagon gate representation of t including I/Os, rotation, const cells, etc.
+     */
     template <typename Lyt>
     [[nodiscard]] static fcn_gate set_up_gate(const Lyt& lyt, const tile<Lyt>& t)
     {