🎨 Incorporated pre-commit fixes

experiments/legalization/legalization.cpp

@@ -49,8 +49,7 @@ Ntk read_ntk(const std::string& name)
 
 int main()  // NOLINT
 {
-    experiments::experiment<std::string, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, bool, bool,
-                            bool>
+    experiments::experiment<std::string, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, bool, bool, bool>
         wiring_reduction_exp{"planarization", "benchmark",       "inputs",         "virt_inputs",
                              "outputs",       "initial nodes",   "nodes buffered", "nodes planarized",
                              "is_planar",     "equivalent(ntk)", "equivalent(lyt)"};
@@ -70,15 +69,15 @@ int main()  // NOLINT
         {
             continue;
         }*/
-        if ( "C432.v" == entry.path().filename().string())
+        if ("C432.v" == entry.path().filename().string())
         {
             continue;
         }
-        if ( "ex4p.v" == entry.path().filename().string())
+        if ("ex4p.v" == entry.path().filename().string())
         {
             continue;
         }
-        if ( "apex1.v" == entry.path().filename().string())
+        if ("apex1.v" == entry.path().filename().string())
         {
             continue;
         }
@@ -144,7 +143,7 @@ int main()  // NOLINT
         }
 
         const auto planarized_b = fiction::node_duplication_planarization<fiction::technology_network>(_b);
-        const auto is_planar = fiction::check_planarity(planarized_b);
+        const auto is_planar    = fiction::check_planarity(planarized_b);
         if (planarized_b.size() > 20000)
         {
             continue;
@@ -169,13 +168,13 @@ int main()  // NOLINT
         fiction::gate_level_drvs(layout, ps_d, &st_d);
 
         const auto miter = mockturtle::miter<mockturtle::klut_network>(planarized_b, layout);
-        bool eq;
+        bool       eq;
         if (miter)
         {
             mockturtle::equivalence_checking_stats st;
 
             const auto ce = mockturtle::equivalence_checking(*miter, {}, &st);
-            eq = ce.value();
+            eq            = ce.value();
         }
         wiring_reduction_exp(entry.path().filename().string(), benchmark_network.num_pis(),
                              planarized_b.num_virtual_pis(), benchmark_network.num_pos(), benchmark_network.num_gates(),
@@ -242,10 +241,9 @@ int main()  // NOLINT
                 {
                     cont = true;
                     std::cout << "Pi is Po\n";
-
                 }
             });
-        if(cont)
+        if (cont)
         {
             continue;
         }
@@ -268,8 +266,9 @@ int main()  // NOLINT
 
         if (planarized_b.size() > 20000)
         {
-            wiring_reduction_exp(benchmark, benchmark_network.num_pis(), planarized_b.num_virtual_pis(), benchmark_network.num_pos(),
-                                 benchmark_network.num_gates(), _b.num_gates(), planarized_b.num_gates(), is_planar, 0, 0);
+            wiring_reduction_exp(benchmark, benchmark_network.num_pis(), planarized_b.num_virtual_pis(),
+                                 benchmark_network.num_pos(), benchmark_network.num_gates(), _b.num_gates(),
+                                 planarized_b.num_gates(), is_planar, 0, 0);
             wiring_reduction_exp.save();
             wiring_reduction_exp.table();
             continue;
@@ -285,14 +284,15 @@ int main()  // NOLINT
 
         fiction::restore_names(benchmark_network, name);
 
-        using gate_lyt =
-            fiction::gate_level_layout<fiction::clocked_layout<fiction::tile_based_layout<fiction::cartesian_layout<>>>>;
+        using gate_lyt = fiction::gate_level_layout<
+            fiction::clocked_layout<fiction::tile_based_layout<fiction::cartesian_layout<>>>>;
 
         fiction::orthogonal_physical_design_stats stats{};
-        using gate_layout = fiction::gate_level_layout<fiction::clocked_layout<fiction::tile_based_layout<fiction::cartesian_layout<fiction::offset::ucoord_t>>>>;
-        auto start = std::chrono::high_resolution_clock::now();
+        using gate_layout = fiction::gate_level_layout<
+            fiction::clocked_layout<fiction::tile_based_layout<fiction::cartesian_layout<fiction::offset::ucoord_t>>>>;
+        auto start  = std::chrono::high_resolution_clock::now();
         auto layout = fiction::orthogonal<gate_layout>(planarized_b, {}, &stats);
-        auto stop = std::chrono::high_resolution_clock::now();
+        auto stop   = std::chrono::high_resolution_clock::now();
 
         std::chrono::duration<double> elapsed = stop - start;
 
@@ -320,22 +320,23 @@ int main()  // NOLINT
                                                                                          "NO";*/
 
         const auto miter = mockturtle::miter<mockturtle::klut_network>(planarized_b, layout);
-        bool eq;
+        bool       eq;
         if (miter)
         {
             mockturtle::equivalence_checking_stats st;
 
             const auto ce = mockturtle::equivalence_checking(*miter, {}, &st);
-            eq = ce.value();
+            eq            = ce.value();
         }
 
         // fiction::debug::write_dot_layout(layout);
         /*fiction::debug::write_dot_network(_b, "ntk_b");
         fiction::debug::write_dot_network(planarized_b, "ntk_p");*/
 
         // log results
-        wiring_reduction_exp(benchmark, benchmark_network.num_pis(), planarized_b.num_virtual_pis(), benchmark_network.num_pos(),
-                             benchmark_network.num_gates(), _b.num_gates(), planarized_b.num_gates(), is_planar, cec_m.value(), eq);
+        wiring_reduction_exp(benchmark, benchmark_network.num_pis(), planarized_b.num_virtual_pis(),
+                             benchmark_network.num_pos(), benchmark_network.num_gates(), _b.num_gates(),
+                             planarized_b.num_gates(), is_planar, cec_m.value(), eq);
 
         wiring_reduction_exp.save();
         wiring_reduction_exp.table();