📝 Update the CHANGELOG (#548)

* Update changelog.rst * Update changelog.rst * Update docs/changelog.rst Co-authored-by: Jan Drewniok <[email protected]> Signed-off-by: simon1hofmann <[email protected]> * Update changelog.rst * Update docs/changelog.rst Co-authored-by: Marcel Walter <[email protected]> Signed-off-by: simon1hofmann <[email protected]> * 🎨 Incorporated pre-commit fixes --------- Signed-off-by: simon1hofmann <[email protected]> Co-authored-by: Jan Drewniok <[email protected]> Co-authored-by: Marcel Walter <[email protected]> Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>
cda-tum · Oct 22, 2024 · f436420 · f436420
1 parent c15e838
commit f436420
Showing 1 changed file with 15 additions and 1 deletion.
diff --git a/docs/changelog.rst b/docs/changelog.rst
@@ -13,7 +13,21 @@ Added
 - Experiments:
     - Script to simulate the critical temperature of SiQAD and Bestagon gates
 - Algorithms:
-    - Added support for different ways of implementing input information in SiDB technology to the BDL input iterator
+    - Physical Design:
+        - QuickCell algorithm for automatic standard cell design in silicon dangling bond logic
+        - Added an option to GOLD to specify discretionary cost objectives
+        - Added a flag to GOLD to enable multi-threading
+        - Added a timeout option to post-layout optimization
+    - Simulation:
+        - Added support for different ways of implementing input information in SiDB technology to the BDL input iterator
+        - Extended BDL input iterator to support different SiDB input representations
+- Documentation:
+    - Added a ``CITATION.cff`` file
+    - Added documentation on our latest papers from IEEE-NANO
+
+Fixed
+#####
+- Addressed some ``clang-tidy`` warnings
 
 
 v0.6.4 - 2024-08-30