✨ Compile time flows and CLI simulation update

cli/CMakeLists.txt

@@ -9,6 +9,26 @@ add_executable(fiction ${SOURCES})
 # Link against the project settings, libfiction and alice
 target_link_libraries(fiction PRIVATE libfiction alice)
 
+# Compile-time decisions on which flows to compile
+
+# Logic synthesis flow
+option(FICTION_LOGIC_SYNTHESIS_FLOW "Enable the logic synthesis flow for the fiction CLI" ON)
+if(FICTION_LOGIC_SYNTHESIS_FLOW)
+  target_compile_definitions(fiction PRIVATE FICTION_LOGIC_SYNTHESIS_FLOW)
+endif()
+
+# Physical design flow
+option(FICTION_PHYSICAL_DESIGN_FLOW "Enable the physical design flow for the fiction CLI" ON)
+if(FICTION_PHYSICAL_DESIGN_FLOW)
+  target_compile_definitions(fiction PRIVATE FICTION_PHYSICAL_DESIGN_FLOW)
+endif()
+
+# Physical simulation flow
+option(FICTION_SIMULATION_FLOW "Enable the physical simulation flow for the fiction CLI" ON)
+if(FICTION_SIMULATION_FLOW)
+  target_compile_definitions(fiction PRIVATE FICTION_SIMULATION_FLOW)
+endif()
+
 # Strip the executable if we are in Release mode
 if(CMAKE_BUILD_TYPE STREQUAL "Release")
   if(CMAKE_STRIP)

cli/cmd/io/read.hpp

@@ -8,6 +8,7 @@
 #include <fiction/io/network_reader.hpp>
 #include <fiction/io/read_fgl_layout.hpp>
 #include <fiction/io/read_fqca_layout.hpp>
+#include <fiction/io/read_sqd_layout.hpp>
 #include <fiction/types.hpp>
 
 #include <alice/alice.hpp>
@@ -23,9 +24,9 @@ namespace alice
  *
  * Currently parses Verilog, AIGER, and BLIF using the lorina parsers.
  *
- * Parses FGL and FQCA via custom reader functions.
- *
  * For more information see: https://github.com/hriener/lorina
+ *
+ * Parses FGL, SQD, and FQCA via custom reader functions.
  */
 class read_command : public command
 {
@@ -40,54 +41,57 @@ class read_command : public command
                        "which will be put into the respective store. Current supported file types are:\n"
                        "Logic networks: Verilog, AIGER, BLIF.\n"
                        "Gate-level layouts: FGL.\n"
-                       "Cell-level layouts: FQCA.\n"
+                       "Cell-level layouts: SQD, FQCA.\n"
                        "In a directory, only files with extension '.v', '.aig', '.blif' are considered.")
     {
         add_option("filename", filename, "Filename or directory")->required();
         add_option("topology", topology,
                    "Topology for gate-level layouts. Can be 'cartesian' or of the form "
                    "'<odd|even>_<row|column>_<cartesian|hex>'");
-        add_flag("--aig,-a", "Parse file as AIG");
-        add_flag("--xag,-x", "Parse file as XAG");
-        add_flag("--mig,-m", "Parse file as MIG");
-        add_flag("--tec,-t", "Parse file as technology network");
-        add_flag("--fgl,-f", "Parse file as fiction gate-level layout");
-        add_flag("--qca,-q", "Parse file as QCA cell-level layout");
-        add_flag("--sort,-s", sort, "Sort networks in given directory by vertex count prior to storing them");
+        add_flag("--aig,-a", "Parse Verilog file as AIG");
+        add_flag("--xag,-x", "Parse Verilog file as XAG");
+        add_flag("--mig,-m", "Parse Verilog file as MIG");
+        add_flag("--tec,-t", "Parse Verilog file as technology network");
+        add_flag("--fgl,-f", "Parse FGL file as fiction gate-level layout");
+        add_flag("--sqd,-s", "Parse SQD file as SiDB cell-level layout");
+        add_flag("--fqca,-q", "Parse FQCA file as QCA cell-level layout");
+        add_flag("--sort", sort, "Sort networks in given directory by node count prior to storing them");
     }
 
   protected:
     /**
-     * Function to perform the read call. Reads Verilog and creates a logic_network.
+     * Function to perform the read call. Reads a network or layout from a file.
      */
     void execute() override
     {
-        const auto store_ntks = [&](auto&& reader)
-        {
-            for (const auto& ln : reader.get_networks(sort))
-            {
-                store<fiction::logic_network_t>().extend() = ln;
-            }
-        };
-
-        if (!is_set("aig") && !is_set("xag") && !is_set("mig") && !is_set("tec") && !is_set("fgl") && !is_set("qca"))
+        if (!is_set("aig") && !is_set("xag") && !is_set("mig") && !is_set("tec") && !is_set("fgl") && !is_set("sqd") &&
+            !is_set("fqca"))
         {
             env->out() << "[e] at least one network or layout type must be specified" << std::endl;
         }
-        else if ((is_set("aig") || is_set("xag") || is_set("mig") || is_set("tec")) && is_set("fql"))
+        else if ((is_set("aig") || is_set("xag") || is_set("mig") || is_set("tec")) && is_set("fgl"))
         {
             env->out() << "[e] cannot parse files as both logic networks and gate-level layouts" << std::endl;
         }
-        else if ((is_set("aig") || is_set("xag") || is_set("mig") || is_set("tec")) && is_set("qca"))
+        else if ((is_set("aig") || is_set("xag") || is_set("mig") || is_set("tec")) &&
+                 (is_set("sqd") || is_set("fqca")))
         {
             env->out() << "[e] cannot parse files as both logic networks and cell-level layouts" << std::endl;
         }
-        else if (is_set("fql") && is_set("qca"))
+        else if (is_set("fgl") && (is_set("sqd") || is_set("fqca")))
         {
             env->out() << "[e] cannot parse files as both gate-level and cell-level layouts" << std::endl;
         }
         else
         {
+            const auto store_ntks = [&](auto&& reader)
+            {
+                for (const auto& ln : reader.get_networks(sort))
+                {
+                    store<fiction::logic_network_t>().extend() = ln;
+                }
+            };
+
             try
             {
                 if (is_set("aig"))
@@ -114,7 +118,7 @@ class read_command : public command
 
                     store_ntks(reader);
                 }
-                if (is_set("fgl") || is_set("qca"))
+                if (is_set("fgl") || is_set("sqd") || is_set("fqca"))
                 {
                     if (std::filesystem::exists(filename))
                     {
@@ -205,7 +209,23 @@ class read_command : public command
                                                << std::endl;
                                 }
                             }
-                            if (is_set("qca"))
+                            else if (is_set("sqd"))
+                            {
+                                try
+                                {
+                                    const auto layout_name = std::filesystem::path{filename}.stem().string();
+
+                                    store<fiction::cell_layout_t>().extend() =
+                                        std::make_shared<fiction::sidb_cell_clk_lyt>(
+                                            fiction::read_sqd_layout<fiction::sidb_cell_clk_lyt>(filename,
+                                                                                                 layout_name));
+                                }
+                                catch (const fiction::sqd_parsing_error& e)
+                                {
+                                    env->out() << e.what() << std::endl;
+                                }
+                            }
+                            else if (is_set("fqca"))
                             {
                                 try
                                 {
@@ -250,7 +270,7 @@ class read_command : public command
             }
             catch (...)
             {
-                env->out() << "[e] no networks or layouts were read" << std::endl;
+                env->out() << "[e] I/O error: no file could be read" << std::endl;
             }
         }
 

cli/cmd/simulation/quickexact.hpp

@@ -0,0 +1,175 @@
+//
+// Created by marcel on 06.12.23.
+//
+
+#ifndef FICTION_CMD_QUICKEXACT_HPP
+#define FICTION_CMD_QUICKEXACT_HPP
+
+#include <fiction/algorithms/simulation/sidb/quickexact.hpp>
+#include <fiction/traits.hpp>
+#include <fiction/types.hpp>
+#include <fiction/utils/name_utils.hpp>
+
+#include <alice/alice.hpp>
+
+#include <variant>
+
+namespace alice
+{
+/**
+ *
+ */
+class quickexact_command : public command
+{
+  public:
+    /**
+     * Standard constructor. Adds descriptive information, options, and flags.
+     *
+     * @param e alice::environment that specifies stores etc.
+     */
+    explicit quickexact_command(const environment::ptr& e) :
+            command(e, "QuickExact is a quick and exact electrostatic ground state simulation algorithm designed "
+                       "specifically for SiDB layouts. It provides a significant performance advantage of more than "
+                       "three orders of magnitude over ExGS from SiQAD.")
+    {
+        add_option("--epsilon_r,-e", physical_params.epsilon_r, "Electric permittivity of the substrate (unit-less)",
+                   true);
+        add_option("--lambda_tf,-l", physical_params.lambda_tf, "Thomas-Fermi screening distance (unit: nm)", true);
+        add_option("--mu_minus,-m", physical_params.mu_minus, "Energy transition level (0/-) (unit: eV)", true);
+        add_option("--base,-b", physical_params.base,
+                   "2-state (neutral/negative) vs. 3-state (positive/neutral/negative) simulation", true);
+        add_option("--global_potential,-g", params.global_potential,
+                   "Global potential applied to the entire layout (unit: V)", true);
+    }
+
+  protected:
+    /**
+     * Function to perform the simulation call.
+     */
+    void execute() override
+    {
+        // reset sim result
+        sim_result = {};
+
+        if (physical_params.epsilon_r <= 0)
+        {
+            env->out() << "[e] epsilon_r must be positive" << std::endl;
+            reset_params();
+            return;
+        }
+
+        if (physical_params.lambda_tf <= 0)
+        {
+            env->out() << "[e] lambda_tf must be positive" << std::endl;
+            reset_params();
+            return;
+        }
+
+        if (physical_params.base != 2 && physical_params.base != 3)
+        {
+            env->out() << "[e] base must be 2 or 3" << std::endl;
+            reset_params();
+            return;
+        }
+
+        auto& s = store<fiction::cell_layout_t>();
+
+        // error case: empty cell layout store
+        if (s.empty())
+        {
+            env->out() << "[w] no cell layout in store" << std::endl;
+            reset_params();
+            return;
+        }
+
+        const auto get_name = [](auto&& lyt_ptr) -> std::string { return fiction::get_name(*lyt_ptr); };
+
+        const auto quickexact = [this, &get_name](auto&& lyt_ptr)
+        {
+            using Lyt = typename std::decay_t<decltype(lyt_ptr)>::element_type;
+
+            if constexpr (fiction::has_sidb_technology_v<Lyt>)
+            {
+                if constexpr (fiction::is_charge_distribution_surface_v<Lyt>)
+                {
+                    env->out() << fmt::format(
+                                      "[w] {} already possesses a charge distribution; no simulation is conducted",
+                                      get_name(lyt_ptr))
+                               << std::endl;
+                }
+                else
+                {
+                    params.physical_parameters = physical_params;
+
+                    sim_result = fiction::quickexact(*lyt_ptr, params);
+
+                    if (sim_result.charge_distributions.empty())
+                    {
+                        env->out() << fmt::format("[e] ground state of {} could not be determined", get_name(lyt_ptr))
+                                   << std::endl;
+                    }
+                    else
+                    {
+                        store<fiction::cell_layout_t>().extend() =
+                            std::make_shared<fiction::cds_sidb_cell_clk_lyt>(sim_result.charge_distributions.front());
+                    }
+                }
+            }
+            else
+            {
+                env->out() << fmt::format("[e] {} is not an SiDB layout", get_name(lyt_ptr)) << std::endl;
+            }
+        };
+
+        std::visit(quickexact, s.current());
+
+        reset_params();
+    }
+
+  private:
+    /**
+     * Physical parameters for the simulation.
+     */
+    fiction::sidb_simulation_parameters physical_params{2, -0.32, 5.6, 5.0};
+    /**
+     * QuickExact parameters.
+     */
+    fiction::quickexact_params<fiction::sidb_cell_clk_lyt> params{};
+    /**
+     * Simulation result.
+     */
+    fiction::sidb_simulation_result<fiction::sidb_cell_clk_lyt> sim_result{};
+
+    /**
+     * Logs the resulting information in a log file.
+     *
+     * @return JSON object containing details about the simulation.
+     */
+    nlohmann::json log() const override
+    {
+        return nlohmann::json{
+            {"Algorithm name", sim_result.algorithm_name},
+            {"Simulation runtime", sim_result.simulation_runtime.count()},
+            {"Physical parameters",
+             {"base", sim_result.physical_parameters.base},
+             {"epsilon_r", sim_result.physical_parameters.epsilon_r},
+             {"lambda_tf", sim_result.physical_parameters.lambda_tf},
+             {"mu_minus", sim_result.physical_parameters.mu_minus}},
+            {"Ground state energy (meV)", sim_result.charge_distributions.front().get_system_energy()},
+            {"Number of stable states", sim_result.charge_distributions.size()}};
+    }
+    /**
+     * Resets the parameters to their default values.
+     */
+    void reset_params()
+    {
+        physical_params = fiction::sidb_simulation_parameters{2, -0.32, 5.6, 5.0};
+        params          = {};
+    }
+};
+
+ALICE_ADD_COMMAND(quickexact, "Simulation")
+
+}  // namespace alice
+
+#endif  // FICTION_CMD_QUICKEXACT_HPP