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🐛 Fixed multiple post_layout_optimization
bugs
#472
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Could you also please adjust the PR description? Currently, it is misformed.
Additionally, it would be great to explain in the description how the bug could be reproduced or triggered. If you want, you could open a respective issue instead and link to that here.
include/fiction/algorithms/physical_design/post_layout_optimization.hpp
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include/fiction/algorithms/physical_design/wiring_reduction.hpp
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…ation.hpp Co-authored-by: Marcel Walter <[email protected]> Signed-off-by: simon1hofmann <[email protected]>
include/fiction/algorithms/physical_design/post_layout_optimization.hpp
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Codecov ReportAll modified and coverable lines are covered by tests ✅
Additional details and impacted files@@ Coverage Diff @@
## main #472 +/- ##
=======================================
Coverage 98.22% 98.23%
=======================================
Files 214 214
Lines 28904 28959 +55
Branches 1369 1380 +11
=======================================
+ Hits 28391 28447 +56
+ Misses 513 512 -1
... and 5 files with indirect coverage changes Continue to review full report in Codecov by Sentry.
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include/fiction/algorithms/physical_design/post_layout_optimization.hpp
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include/fiction/algorithms/physical_design/wiring_reduction.hpp
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include/fiction/algorithms/physical_design/wiring_reduction.hpp
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post_layout_optimization
bugspost_layout_optimization
bugs
Description
Fixed two bugs in
post_layout_optimization
:Fixed a special case in
wiring_reduction
for double fanin gates:In a layout, a structure like this can appear:
Using A*, two paths can be found for deletion, which leads to:
+ → &
Therefore, the wire to the left of the AND gate is blocked so only one path can be found.
Checklist: