🔧 Attempt to calm down clang-tidy

.clang-tidy

@@ -15,6 +15,7 @@ Checks: |
   -cppcoreguidelines-avoid-magic-numbers,
   -cppcoreguidelines-non-private-member-variables-in-classes,
   -cppcoreguidelines-pro-type-union-access,
+  -cppcoreguidelines-avoid-const-or-ref-data-members,
   google-*,
   -google-readability-todo,
   -google-build-using-namespace,
@@ -40,6 +41,8 @@ Checks: |
 CheckOptions:
   - key: cppcoreguidelines-avoid-do-while.IgnoreMacros
     value: "true"
+  - key: misc-include-cleaner.IgnoreHeaders
+    value: ".*/experiments.hpp;.*/fiction_experiments.hpp;.*/fmt/.*"
   - key: readability-identifier-naming.NamespaceCase
     value: lower_case
   - key: readability-identifier-naming.ClassCase

experiments/bestagon/bestagon.cpp

@@ -15,7 +15,6 @@
 #include <fiction/technology/cell_technologies.hpp>           // cell implementations
 #include <fiction/technology/sidb_bestagon_library.hpp>       // a pre-defined SiDB gate library
 #include <fiction/technology/technology_mapping_library.hpp>  // pre-defined gate types for technology mapping
-#include <fiction/traits.hpp>                                 // traits for type-checking
 #include <fiction/types.hpp>                                  // pre-defined types suitable for the FCN domain
 
 #include <fmt/format.h>                                        // output formatting
@@ -28,7 +27,6 @@
 #include <mockturtle/algorithms/node_resynthesis/xag_npn.hpp>  // NPN databases for cut rewriting of XAGs and AIGs
 #include <mockturtle/io/genlib_reader.hpp>                     // call-backs to read Genlib files into gate libraries
 #include <mockturtle/io/verilog_reader.hpp>                    // call-backs to read Verilog files into networks
-#include <mockturtle/networks/klut.hpp>                        // k-LUT network
 #include <mockturtle/networks/xag.hpp>                         // XOR-AND-inverter graphs
 #include <mockturtle/utils/tech_library.hpp>                   // technology library utils
 #include <mockturtle/views/depth_view.hpp>                     // to determine network levels

experiments/defect_aware_physical_design/defect_aware_physical_design.cpp

@@ -39,6 +39,7 @@
 
 #include <cstdint>
 #include <cstdlib>
+#include <iostream>
 #include <sstream>
 #include <string>
 #include <unordered_set>

experiments/post_layout_optimization/post_layout_optimization.cpp

@@ -1,12 +1,15 @@
+#include "fiction/layouts/bounding_box.hpp"
 #include "fiction_experiments.hpp"
 
 #include <fiction/algorithms/physical_design/orthogonal.hpp>                // scalable heuristic for physical design
 #include <fiction/algorithms/physical_design/post_layout_optimization.hpp>  // post-layout optimization
 #include <fiction/algorithms/properties/critical_path_length_and_throughput.hpp>  // critical path and throughput calculations
 #include <fiction/algorithms/verification/equivalence_checking.hpp>               // SAT-based equivalence checking
 #include <fiction/io/network_reader.hpp>                                          // read networks from files
+#include <fiction/types.hpp>                                                      // types suitable for the FCN domain
 
-#include <fmt/format.h>  // output formatting
+#include <fmt/format.h>                    // output formatting
+#include <mockturtle/utils/stopwatch.hpp>  // runtime measurements
 
 #include <cstdint>
 #include <cstdlib>