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WIP: Fix linter warnings related to undriven nets #196

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WIP: Fix linter warnings related to undriven nets #196

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6 changes: 0 additions & 6 deletions design/el2_veer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -392,7 +392,7 @@



logic [63:0] hwdata_nc;

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design/el2_veer.sv:395:-   logic [63:0]                  hwdata_nc;
design/el2_veer.sv:396:-   //----------------------------------------------------------------------
design/el2_veer.sv:397:-   //
design/el2_veer.sv:398:-   //----------------------------------------------------------------------
design/el2_veer.sv:399:-
design/el2_veer.sv:400:-   logic                         ifu_pmu_instr_aligned;
design/el2_veer.sv:401:-   logic                         ifu_ic_error_start;
design/el2_veer.sv:402:-   logic                         ifu_iccm_dma_rd_ecc_single_err;
design/el2_veer.sv:403:-   logic                         ifu_iccm_rd_ecc_single_err;
design/el2_veer.sv:404:-   logic                         ifu_iccm_rd_ecc_double_err;
design/el2_veer.sv:405:-   logic                         lsu_dccm_rd_ecc_single_err;
design/el2_veer.sv:406:-   logic                         lsu_dccm_rd_ecc_double_err;
design/el2_veer.sv:407:-
design/el2_veer.sv:408:-   logic                         lsu_axi_awready_ahb;
design/el2_veer.sv:409:-   logic                         lsu_axi_wready_ahb;
design/el2_veer.sv:410:-   logic                         lsu_axi_bvalid_ahb;
design/el2_veer.sv:411:-   logic                         lsu_axi_bready_ahb;
design/el2_veer.sv:412:-   logic [1:0]                   lsu_axi_bresp_ahb;
design/el2_veer.sv:413:-   logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_bid_ahb;
design/el2_veer.sv:414:-   logic                         lsu_axi_arready_ahb;
design/el2_veer.sv:415:-   logic                         lsu_axi_rvalid_ahb;
design/el2_veer.sv:416:-   logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_rid_ahb;
design/el2_veer.sv:417:-   logic [63:0]                  lsu_axi_rdata_ahb;
design/el2_veer.sv:418:-   logic [1:0]                   lsu_axi_rresp_ahb;
design/el2_veer.sv:419:-   logic                         lsu_axi_rlast_ahb;
design/el2_veer.sv:420:-
design/el2_veer.sv:421:-   logic                         lsu_axi_awready_int;
design/el2_veer.sv:422:-   logic                         lsu_axi_wready_int;
design/el2_veer.sv:423:-   logic                         lsu_axi_bvalid_int;
design/el2_veer.sv:424:-   logic [1:0]                   lsu_axi_bresp_int;
design/el2_veer.sv:425:-   logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_bid_int;
design/el2_veer.sv:426:-   logic                         lsu_axi_arready_int;
design/el2_veer.sv:427:-   logic                         lsu_axi_rvalid_int;
design/el2_veer.sv:428:-   logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_rid_int;
design/el2_veer.sv:429:-   logic [63:0]                  lsu_axi_rdata_int;
design/el2_veer.sv:430:-   logic [1:0]                   lsu_axi_rresp_int;
design/el2_veer.sv:431:-   logic                         lsu_axi_rlast_int;
design/el2_veer.sv:432:-
design/el2_veer.sv:433:-   logic                         ifu_axi_awready_ahb;
design/el2_veer.sv:434:-   logic                         ifu_axi_wready_ahb;
design/el2_veer.sv:435:-   logic                         ifu_axi_bvalid_ahb;
design/el2_veer.sv:436:-   logic                         ifu_axi_bready_ahb;
design/el2_veer.sv:437:-   logic [1:0]                   ifu_axi_bresp_ahb;
design/el2_veer.sv:438:-   logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_ahb;
design/el2_veer.sv:439:-   logic                         ifu_axi_arready_ahb;
design/el2_veer.sv:440:-   logic                         ifu_axi_rvalid_ahb;
design/el2_veer.sv:441:-   logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_ahb;
design/el2_veer.sv:442:-   logic [63:0]                  ifu_axi_rdata_ahb;
design/el2_veer.sv:443:-   logic [1:0]                   ifu_axi_rresp_ahb;
design/el2_veer.sv:444:-   logic                         ifu_axi_rlast_ahb;
design/el2_veer.sv:445:-
design/el2_veer.sv:446:-   logic                         ifu_axi_awready_int;
design/el2_veer.sv:447:-   logic                         ifu_axi_wready_int;
design/el2_veer.sv:448:-   logic                         ifu_axi_bvalid_int;
design/el2_veer.sv:449:-   logic [1:0]                   ifu_axi_bresp_int;
design/el2_veer.sv:450:-   logic [pt.IFU_BUS
//----------------------------------------------------------------------
//
//----------------------------------------------------------------------
Expand Down Expand Up @@ -421,7 +421,6 @@
logic lsu_axi_awready_int;
logic lsu_axi_wready_int;
logic lsu_axi_bvalid_int;
logic lsu_axi_bready_int;
logic [1:0] lsu_axi_bresp_int;
logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid_int;
logic lsu_axi_arready_int;
Expand All @@ -447,7 +446,6 @@
logic ifu_axi_awready_int;
logic ifu_axi_wready_int;
logic ifu_axi_bvalid_int;
logic ifu_axi_bready_int;
logic [1:0] ifu_axi_bresp_int;
logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid_int;
logic ifu_axi_arready_int;
Expand All @@ -473,7 +471,6 @@
logic sb_axi_awready_int;
logic sb_axi_wready_int;
logic sb_axi_bvalid_int;
logic sb_axi_bready_int;
logic [1:0] sb_axi_bresp_int;
logic [pt.SB_BUS_TAG-1:0] sb_axi_bid_int;
logic sb_axi_arready_int;
Expand Down Expand Up @@ -1004,7 +1001,7 @@
.*
);

if (pt.BUILD_AHB_LITE == 1) begin: Gen_AXI_To_AHB

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Raw Output:
design/el2_veer.sv:1004:-   if (pt.BUILD_AHB_LITE == 1) begin: Gen_AXI_To_AHB
design/el2_veer.sv:1005:-
design/el2_veer.sv:1006:-      // AXI4 -> AHB Gasket for LSU
design/el2_veer.sv:1007:-      axi4_to_ahb #(.pt(pt),
design/el2_veer.sv:1008:-                    .TAG(pt.LSU_BUS_TAG)) lsu_axi4_to_ahb (
design/el2_veer.sv:1009:-
design/el2_veer.sv:1010:-         .clk(free_l2clk),
design/el2_veer.sv:1011:-         .free_clk(free_clk),
design/el2_veer.sv:1012:-         .rst_l(core_rst_l),
design/el2_veer.sv:1013:-         .clk_override(dec_tlu_bus_clk_override),
design/el2_veer.sv:1014:-         .bus_clk_en(lsu_bus_clk_en),
design/el2_veer.sv:1015:-         .dec_tlu_force_halt(dec_tlu_force_halt),
design/el2_veer.sv:1016:-
design/el2_veer.sv:1017:-         // AXI Write Channels
design/el2_veer.sv:1018:-         .axi_awvalid(lsu_axi_awvalid),
design/el2_veer.sv:1019:-         .axi_awready(lsu_axi_awready_ahb),
design/el2_veer.sv:1020:-         .axi_awid(lsu_axi_awid[pt.LSU_BUS_TAG-1:0]),
design/el2_veer.sv:1021:-         .axi_awaddr(lsu_axi_awaddr[31:0]),
design/el2_veer.sv:1022:-         .axi_awsize(lsu_axi_awsize[2:0]),
design/el2_veer.sv:1023:-         .axi_awprot(lsu_axi_awprot[2:0]),
design/el2_veer.sv:1024:-
design/el2_veer.sv:1025:-         .axi_wvalid(lsu_axi_wvalid),
design/el2_veer.sv:1026:-         .axi_wready(lsu_axi_wready_ahb),
design/el2_veer.sv:1027:-         .axi_wdata(lsu_axi_wdata[63:0]),
design/el2_veer.sv:1028:-         .axi_wstrb(lsu_axi_wstrb[7:0]),
design/el2_veer.sv:1029:-         .axi_wlast(lsu_axi_wlast),
design/el2_veer.sv:1030:-
design/el2_veer.sv:1031:-         .axi_bvalid(lsu_axi_bvalid_ahb),
design/el2_veer.sv:1032:-         .axi_bready(lsu_axi_bready),
design/el2_veer.sv:1033:-         .axi_bresp(lsu_axi_bresp_ahb[1:0]),
design/el2_veer.sv:1034:-         .axi_bid(lsu_axi_bid_ahb[pt.LSU_BUS_TAG-1:0]),
design/el2_veer.sv:1035:-
design/el2_veer.sv:1036:-         // AXI Read Channels
design/el2_veer.sv:1037:-         .axi_arvalid(lsu_axi_arvalid),
design/el2_veer.sv:1038:-         .axi_arready(lsu_axi_arready_ahb),
design/el2_veer.sv:1039:-         .axi_arid(lsu_axi_arid[pt.LSU_BUS_TAG-1:0]),
design/el2_veer.sv:1040:-         .axi_araddr(lsu_axi_araddr[31:0]),
design/el2_veer.sv:1041:-         .axi_arsize(lsu_axi_arsize[2:0]),
design/el2_veer.sv:1042:-         .axi_arprot(lsu_axi_arprot[2:0]),
design/el2_veer.sv:1043:-
design/el2_veer.sv:1044:-         .axi_rvalid(lsu_axi_rvalid_ahb),
design/el2_veer.sv:1045:-         .axi_rready(lsu_axi_rready),
design/el2_veer.sv:1046:-         .axi_rid(lsu_axi_rid_ahb[pt.LSU_BUS_TAG-1:0]),
design/el2_veer.sv:1047:-         .axi_rdata(lsu_axi_rdata_ahb[63:0]),
design/el2_veer.sv:1048:-         .axi_rresp(lsu_axi_rresp_ahb[1:0]),
design/el2_veer.sv:1049:-         .axi_rlast(lsu_axi_rlast_ahb),
design/el2_veer.sv:1050:-
design/el2_veer.sv:1051:-         // AHB-LITE signals
design/el2_veer.sv:1052:-         .ahb_haddr(lsu_haddr[31:0]),
design/el2_veer.sv:1053:-         .ahb_hburst(lsu_hburst),
design/el2_veer.sv:1054:-         .ahb_hmastlock(lsu_hmastlock),
design/el2_veer.sv:1055:-         .ahb_hprot(lsu_hprot[3:0]),
design/el2_veer.sv:1056:-         .ahb_hsize(lsu_hsize[2:0]),
design/el2_veer.sv:1057:-         .ahb_htrans(lsu_htrans[1:0]),
design/el2_veer.sv:1058:-         .ahb_hwrite(lsu_hwrite),
design/el2_veer.sv:1059:-         .ahb_hwdata(lsu_hwdata[63:0]),
design/el2_veer.sv:1060:-
design/el2_veer.sv:1061:-         .ahb_hrdata(lsu_hrdata[63:0]),
design/el2_veer.sv:1062:-         .ahb_hready(lsu_hready),
design/el2_veer.sv:1063:-         .ahb_hresp(lsu_hresp),
design/el2_veer.sv:1064:-
design/el2_veer.sv:1065:-         .*
design/el2_veer.sv:1066:-      );
design/el2_veer.sv:1067:-
design/el2_veer.sv:1068:-      axi4_to_ahb #(.pt(pt),
design/el2_veer.sv:1069:-                    .TAG(pt.IFU_BUS_TAG)) ifu_axi4_to_ahb (
design/el2_veer.sv:1070:-         .clk(free_l2clk),
design/el2_veer.sv:1071:-         .free_clk(free_clk),
design/el2_veer.sv:1072:-         .rst_l(core_rst_l),
design/el2_veer.sv:1

// AXI4 -> AHB Gasket for LSU
axi4_to_ahb #(.pt(pt),
Expand Down Expand Up @@ -1256,7 +1253,6 @@
assign lsu_axi_awready_int = pt.BUILD_AHB_LITE ? lsu_axi_awready_ahb : lsu_axi_awready;
assign lsu_axi_wready_int = pt.BUILD_AHB_LITE ? lsu_axi_wready_ahb : lsu_axi_wready;
assign lsu_axi_bvalid_int = pt.BUILD_AHB_LITE ? lsu_axi_bvalid_ahb : lsu_axi_bvalid;
assign lsu_axi_bready_int = pt.BUILD_AHB_LITE ? lsu_axi_bready_ahb : lsu_axi_bready;
assign lsu_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? lsu_axi_bresp_ahb[1:0] : lsu_axi_bresp[1:0];
assign lsu_axi_bid_int[pt.LSU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? lsu_axi_bid_ahb[pt.LSU_BUS_TAG-1:0] : lsu_axi_bid[pt.LSU_BUS_TAG-1:0];
assign lsu_axi_arready_int = pt.BUILD_AHB_LITE ? lsu_axi_arready_ahb : lsu_axi_arready;
Expand All @@ -1269,7 +1265,6 @@
assign ifu_axi_awready_int = pt.BUILD_AHB_LITE ? ifu_axi_awready_ahb : ifu_axi_awready;
assign ifu_axi_wready_int = pt.BUILD_AHB_LITE ? ifu_axi_wready_ahb : ifu_axi_wready;
assign ifu_axi_bvalid_int = pt.BUILD_AHB_LITE ? ifu_axi_bvalid_ahb : ifu_axi_bvalid;
assign ifu_axi_bready_int = pt.BUILD_AHB_LITE ? ifu_axi_bready_ahb : ifu_axi_bready;
assign ifu_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? ifu_axi_bresp_ahb[1:0] : ifu_axi_bresp[1:0];
assign ifu_axi_bid_int[pt.IFU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? ifu_axi_bid_ahb[pt.IFU_BUS_TAG-1:0] : ifu_axi_bid[pt.IFU_BUS_TAG-1:0];
assign ifu_axi_arready_int = pt.BUILD_AHB_LITE ? ifu_axi_arready_ahb : ifu_axi_arready;
Expand All @@ -1282,7 +1277,6 @@
assign sb_axi_awready_int = pt.BUILD_AHB_LITE ? sb_axi_awready_ahb : sb_axi_awready;
assign sb_axi_wready_int = pt.BUILD_AHB_LITE ? sb_axi_wready_ahb : sb_axi_wready;
assign sb_axi_bvalid_int = pt.BUILD_AHB_LITE ? sb_axi_bvalid_ahb : sb_axi_bvalid;
assign sb_axi_bready_int = pt.BUILD_AHB_LITE ? sb_axi_bready_ahb : sb_axi_bready;
assign sb_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? sb_axi_bresp_ahb[1:0] : sb_axi_bresp[1:0];
assign sb_axi_bid_int[pt.SB_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? sb_axi_bid_ahb[pt.SB_BUS_TAG-1:0] : sb_axi_bid[pt.SB_BUS_TAG-1:0];
assign sb_axi_arready_int = pt.BUILD_AHB_LITE ? sb_axi_arready_ahb : sb_axi_arready;
Expand Down
3 changes: 3 additions & 0 deletions design/exu/el2_exu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -322,7 +322,7 @@
assign after_flush_eghr[pt.BHT_GHR_SIZE-1:0] = (i0_flush_upper_x & ~dec_tlu_flush_lower_r) ? ghr_d[pt.BHT_GHR_SIZE-1:0] : ghr_x[pt.BHT_GHR_SIZE-1:0];


assign exu_mp_pkt.valid = final_predict_mp.valid;

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Raw Output:
design/exu/el2_exu.sv:325:-   assign exu_mp_pkt.valid                                  =  final_predict_mp.valid;
design/exu/el2_exu.sv:326:-   assign exu_mp_pkt.way                                    =  final_predict_mp.way;
design/exu/el2_exu.sv:327:-   assign exu_mp_pkt.misp                                   =  final_predict_mp.misp;
design/exu/el2_exu.sv:328:-   assign exu_mp_pkt.pcall                                  =  final_predict_mp.pcall;
design/exu/el2_exu.sv:329:-   assign exu_mp_pkt.pja                                    =  final_predict_mp.pja;
design/exu/el2_exu.sv:330:-   assign exu_mp_pkt.pret                                   =  final_predict_mp.pret;
design/exu/el2_exu.sv:331:-   assign exu_mp_pkt.ataken                                 =  final_predict_mp.ataken;
design/exu/el2_exu.sv:332:-   assign exu_mp_pkt.boffset                                =  final_predict_mp.boffset;
design/exu/el2_exu.sv:333:-   assign exu_mp_pkt.pc4                                    =  final_predict_mp.pc4;
design/exu/el2_exu.sv:334:-   assign exu_mp_pkt.hist[1:0]                              =  final_predict_mp.hist[1:0];
design/exu/el2_exu.sv:335:-   assign exu_mp_pkt.toffset[11:0]                          =  final_predict_mp.toffset[11:0];
design/exu/el2_exu.sv:336:-   assign exu_mp_pkt.br_start_error                         =  final_predict_mp.br_start_error;
design/exu/el2_exu.sv:337:-   assign exu_mp_pkt.br_error                               =  final_predict_mp.br_error;
design/exu/el2_exu.sv:338:-   assign exu_mp_pkt.prett[31:1]                            =  final_predict_mp.prett[31:1];
design/exu/el2_exu.sv:407:+    assign exu_mp_pkt.valid = final_predict_mp.valid;
design/exu/el2_exu.sv:408:+    assign exu_mp_pkt.way = final_predict_mp.way;
design/exu/el2_exu.sv:409:+    assign exu_mp_pkt.misp = final_predict_mp.misp;
design/exu/el2_exu.sv:410:+    assign exu_mp_pkt.pcall = final_predict_mp.pcall;
design/exu/el2_exu.sv:411:+    assign exu_mp_pkt.pja = final_predict_mp.pja;
design/exu/el2_exu.sv:412:+    assign exu_mp_pkt.pret = final_predict_mp.pret;
design/exu/el2_exu.sv:413:+    assign exu_mp_pkt.ataken = final_predict_mp.ataken;
design/exu/el2_exu.sv:414:+    assign exu_mp_pkt.boffset = final_predict_mp.boffset;
design/exu/el2_exu.sv:415:+    assign exu_mp_pkt.pc4 = final_predict_mp.pc4;
design/exu/el2_exu.sv:416:+    assign exu_mp_pkt.hist[1:0] = final_predict_mp.hist[1:0];
design/exu/el2_exu.sv:417:+    assign exu_mp_pkt.toffset[11:0] = final_predict_mp.toffset[11:0];
design/exu/el2_exu.sv:418:+    assign exu_mp_pkt.br_start_error = final_predict_mp.br_start_error;
design/exu/el2_exu.sv:419:+    assign exu_mp_pkt.br_error = final_predict_mp.br_error;
design/exu/el2_exu.sv:420:+    assign exu_mp_pkt.prett[31:1] = final_predict_mp.prett[31:1];
assign exu_mp_pkt.way = final_predict_mp.way;
assign exu_mp_pkt.misp = final_predict_mp.misp;
assign exu_mp_pkt.pcall = final_predict_mp.pcall;
Expand All @@ -333,6 +333,9 @@
assign exu_mp_pkt.pc4 = final_predict_mp.pc4;
assign exu_mp_pkt.hist[1:0] = final_predict_mp.hist[1:0];
assign exu_mp_pkt.toffset[11:0] = final_predict_mp.toffset[11:0];
assign exu_mp_pkt.br_start_error = final_predict_mp.br_start_error;
assign exu_mp_pkt.br_error = final_predict_mp.br_error;
assign exu_mp_pkt.prett[31:1] = final_predict_mp.prett[31:1];

assign exu_mp_fghr[pt.BHT_GHR_SIZE-1:0] = after_flush_eghr[pt.BHT_GHR_SIZE-1:0];
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3 changes: 1 addition & 2 deletions design/ifu/el2_ifu_bp_ctl.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -793,14 +793,13 @@
assign wr0_en[j] = ((btb_fa_wr_addr0[BTB_FA_INDEX:0] == j) & (exu_mp_valid_write & ~exu_mp_pkt.way)) |
((dec_fa_error_index == j) & dec_tlu_error_wb);

rvdffe #(BTB_DWIDTH) btb_fa (.*, .clk(clk),

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Raw Output:
design/ifu/el2_ifu_bp_ctl.sv:796:-      rvdffe #(BTB_DWIDTH) btb_fa (.*, .clk(clk),
design/ifu/el2_ifu_bp_ctl.sv:797:-                                   .en  (wr0_en[j]),
design/ifu/el2_ifu_bp_ctl.sv:798:-                                   .din (btb_wr_data[BTB_DWIDTH-1:0]),
design/ifu/el2_ifu_bp_ctl.sv:799:-                                   .dout(btbdata[j]));
design/ifu/el2_ifu_bp_ctl.sv:800:-   end // block: BTB_FAFLOPS
design/ifu/el2_ifu_bp_ctl.sv:912:+      rvdffe #(BTB_DWIDTH) btb_fa (
design/ifu/el2_ifu_bp_ctl.sv:913:+          .*,
design/ifu/el2_ifu_bp_ctl.sv:914:+          .clk (clk),
design/ifu/el2_ifu_bp_ctl.sv:915:+          .en  (wr0_en[j]),
design/ifu/el2_ifu_bp_ctl.sv:916:+          .din (btb_wr_data[BTB_DWIDTH-1:0]),
design/ifu/el2_ifu_bp_ctl.sv:917:+          .dout(btbdata[j])
design/ifu/el2_ifu_bp_ctl.sv:918:+      );
design/ifu/el2_ifu_bp_ctl.sv:919:+    end  // block: BTB_FAFLOPS
.en (wr0_en[j]),
.din (btb_wr_data[BTB_DWIDTH-1:0]),
.dout(btbdata[j]));
end // block: BTB_FAFLOPS

assign ifu_bp_fa_index_f[1] = hit1 ? hit1_index : '0;
assign ifu_bp_fa_index_f[0] = hit0 ? hit0_index : '0;
assign ifu_bp_fa_index_f = {hit1 ? hit1_index : '0, hit0 ? hit0_index : '0};
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assign btb_used_reset = &btb_used[pt.BTB_SIZE-1:0];
assign btb_used_ns[pt.BTB_SIZE-1:0] = ({pt.BTB_SIZE{vwayhit_f[1]}} & (32'b1 << hit1_index[BTB_FA_INDEX:0])) |
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5 changes: 3 additions & 2 deletions design/ifu/el2_ifu_ic_mem.sv
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Expand Up @@ -766,7 +766,7 @@

logic [pt.ICACHE_BANKS_WAY-1:0][3:0] ic_parerr_bank;

for (genvar i=0; i < pt.ICACHE_BANKS_WAY ; i++) begin : ic_par_error

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Raw Output:
design/ifu/el2_ifu_ic_mem.sv:769:-  for (genvar i=0; i < pt.ICACHE_BANKS_WAY ; i++) begin : ic_par_error
design/ifu/el2_ifu_ic_mem.sv:770:-    assign bank_check_en[i]    = |ic_rd_hit[pt.ICACHE_NUM_WAYS-1:0] & ((i==0) | (~ic_cacheline_wrap_ff & (ic_b_rden_ff[pt.ICACHE_BANKS_WAY-1:0] == {pt.ICACHE_BANKS_WAY{1'b1}})));  // always check the lower address bank, and drop the upper address bank on a CL wrap
design/ifu/el2_ifu_ic_mem.sv:771:-     for (genvar j=0; j<4; j++)  begin : parity
design/ifu/el2_ifu_ic_mem.sv:772:-      rveven_paritycheck pchk (
design/ifu/el2_ifu_ic_mem.sv:773:-                           .data_in   (wb_dout_ecc_bank[i][16*(j+1)-1: 16*j]),
design/ifu/el2_ifu_ic_mem.sv:774:-                           .parity_in (wb_dout_ecc_bank[i][64+j]),
design/ifu/el2_ifu_ic_mem.sv:775:-                           .parity_err(ic_parerr_bank[i][j] )
design/ifu/el2_ifu_ic_mem.sv:776:-                           );
design/ifu/el2_ifu_ic_mem.sv:777:-        end
design/ifu/el2_ifu_ic_mem.sv:778:-     assign ic_eccerr [i] = '0 ;
design/ifu/el2_ifu_ic_mem.sv:779:-  end
design/ifu/el2_ifu_ic_mem.sv:771:+    for (genvar i = 0; i < pt.ICACHE_BANKS_WAY; i++) begin : ic_par_error
design/ifu/el2_ifu_ic_mem.sv:772:+      assign bank_check_en[i]    = |ic_rd_hit[pt.ICACHE_NUM_WAYS-1:0] & ((i==0) | (~ic_cacheline_wrap_ff & (ic_b_rden_ff[pt.ICACHE_BANKS_WAY-1:0] == {pt.ICACHE_BANKS_WAY{1'b1}})));  // always check the lower address bank, and drop the upper address bank on a CL wrap
design/ifu/el2_ifu_ic_mem.sv:773:+      for (genvar j = 0; j < 4; j++) begin : parity
design/ifu/el2_ifu_ic_mem.sv:774:+        rveven_paritycheck pchk (
design/ifu/el2_ifu_ic_mem.sv:775:+            .data_in   (wb_dout_ecc_bank[i][16*(j+1)-1: 16*j]),
design/ifu/el2_ifu_ic_mem.sv:776:+            .parity_in (wb_dout_ecc_bank[i][64+j]),
design/ifu/el2_ifu_ic_mem.sv:777:+            .parity_err(ic_parerr_bank[i][j] )
design/ifu/el2_ifu_ic_mem.sv:778:+        );
design/ifu/el2_ifu_ic_mem.sv:779:+      end
design/ifu/el2_ifu_ic_mem.sv:780:+      assign ic_eccerr[i] = '0;
design/ifu/el2_ifu_ic_mem.sv:781:+    end
assign bank_check_en[i] = |ic_rd_hit[pt.ICACHE_NUM_WAYS-1:0] & ((i==0) | (~ic_cacheline_wrap_ff & (ic_b_rden_ff[pt.ICACHE_BANKS_WAY-1:0] == {pt.ICACHE_BANKS_WAY{1'b1}}))); // always check the lower address bank, and drop the upper address bank on a CL wrap
for (genvar j=0; j<4; j++) begin : parity
rveven_paritycheck pchk (
Expand All @@ -778,8 +778,9 @@
assign ic_eccerr [i] = '0 ;
end

assign ic_parerr[1] = (|ic_parerr_bank[1][3:0]) & bank_check_en[1];
assign ic_parerr[0] = (|ic_parerr_bank[0][3:0]) & bank_check_en[0];
assign ic_parerr = {
(|ic_parerr_bank[1][3:0]) & bank_check_en[1], (|ic_parerr_bank[0][3:0]) & bank_check_en[0]
};
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end // else: !if( pt.ICACHE_ECC )
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5 changes: 4 additions & 1 deletion design/lsu/el2_lsu_dccm_ctl.sv
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Expand Up @@ -157,7 +157,7 @@
);


localparam DCCM_WIDTH_BITS = $clog2(pt.DCCM_BYTE_WIDTH);

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Raw Output:
design/lsu/el2_lsu_dccm_ctl.sv:160:-   localparam DCCM_WIDTH_BITS = $clog2(pt.DCCM_BYTE_WIDTH);
design/lsu/el2_lsu_dccm_ctl.sv:161:-
design/lsu/el2_lsu_dccm_ctl.sv:162:-   logic                           lsu_dccm_rden_d, lsu_dccm_wren_d;
design/lsu/el2_lsu_dccm_ctl.sv:163:-   logic                           ld_single_ecc_error_lo_r, ld_single_ecc_error_hi_r;
design/lsu/el2_lsu_dccm_ctl.sv:164:-   logic                           ld_single_ecc_error_lo_r_ns, ld_single_ecc_error_hi_r_ns;
design/lsu/el2_lsu_dccm_ctl.sv:165:-   logic                           ld_single_ecc_error_lo_r_ff, ld_single_ecc_error_hi_r_ff;
design/lsu/el2_lsu_dccm_ctl.sv:166:-   logic                           lsu_double_ecc_error_r_ff;
design/lsu/el2_lsu_dccm_ctl.sv:167:-   logic [pt.DCCM_BITS-1:0]        ld_sec_addr_lo_r_ff, ld_sec_addr_hi_r_ff;
design/lsu/el2_lsu_dccm_ctl.sv:168:-   logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_lo_r_in, store_data_hi_r_in ;
design/lsu/el2_lsu_dccm_ctl.sv:169:-   logic [63:0]                    picm_rd_data_m;
design/lsu/el2_lsu_dccm_ctl.sv:170:-
design/lsu/el2_lsu_dccm_ctl.sv:171:-   logic                           dccm_wr_bypass_d_m_hi, dccm_wr_bypass_d_r_hi;
design/lsu/el2_lsu_dccm_ctl.sv:172:-   logic                           dccm_wr_bypass_d_m_lo, dccm_wr_bypass_d_r_lo;
design/lsu/el2_lsu_dccm_ctl.sv:173:-   logic                           kill_ecc_corr_lo_r, kill_ecc_corr_hi_r;
design/lsu/el2_lsu_dccm_ctl.sv:174:-
design/lsu/el2_lsu_dccm_ctl.sv:175:-    // byte_en flowing down
design/lsu/el2_lsu_dccm_ctl.sv:176:-   logic [3:0]                     store_byteen_m ,store_byteen_r;
design/lsu/el2_lsu_dccm_ctl.sv:177:-   logic [7:0]                     store_byteen_ext_m, store_byteen_ext_r;
design/lsu/el2_lsu_dccm_ctl.sv:178:-
design/lsu/el2_lsu_dccm_ctl.sv:179:-   if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U_Plus1_1
design/lsu/el2_lsu_dccm_ctl.sv:180:-      logic [63:0]  lsu_rdata_r, lsu_rdata_corr_r;
design/lsu/el2_lsu_dccm_ctl.sv:181:-      logic [63:0]  dccm_rdata_r, dccm_rdata_corr_r;
design/lsu/el2_lsu_dccm_ctl.sv:182:-      logic [63:0]  stbuf_fwddata_r;
design/lsu/el2_lsu_dccm_ctl.sv:183:-      logic [7:0]   stbuf_fwdbyteen_r;
design/lsu/el2_lsu_dccm_ctl.sv:184:-      logic [31:0]  stbuf_fwddata_lo_r, stbuf_fwddata_hi_r;
design/lsu/el2_lsu_dccm_ctl.sv:185:-      logic [3:0]   stbuf_fwdbyteen_lo_r, stbuf_fwdbyteen_hi_r;
design/lsu/el2_lsu_dccm_ctl.sv:186:-      logic [31:0]  lsu_rdata_lo_r, lsu_rdata_hi_r;
design/lsu/el2_lsu_dccm_ctl.sv:187:-      logic [63:0]  picm_rd_data_r;
design/lsu/el2_lsu_dccm_ctl.sv:188:-      logic [63:0]  lsu_ld_data_r_shift;
design/lsu/el2_lsu_dccm_ctl.sv:189:-      logic [63:32] lsu_ld_data_r_nc, lsu_ld_data_corr_r_nc;
design/lsu/el2_lsu_dccm_ctl.sv:190:-      logic [2:0]   dma_mem_tag_r;
design/lsu/el2_lsu_dccm_ctl.sv:191:-      logic         stbuf_fwddata_en;
design/lsu/el2_lsu_dccm_ctl.sv:192:-
design/lsu/el2_lsu_dccm_ctl.sv:193:-      assign dccm_dma_rvalid      = lsu_pkt_r.valid & lsu_pkt_r.load & lsu_pkt_r.dma;
design/lsu/el2_lsu_dccm_ctl.sv:194:-      assign dccm_dma_ecc_error   = lsu_double_ecc_error_r;
design/lsu/el2_lsu_dccm_ctl.sv:195:-      assign dccm_dma_rtag[2:0]   = dma_mem_tag_r[2:0];
design/lsu/el2_lsu_dccm_ctl.sv:196:-      assign dccm_dma_rdata[63:0] = ldst_dual_r ? lsu_rdata_corr_r[63:0] : {2{lsu_rdata_corr_r[31:0]}};
design/lsu/el2_lsu_dccm_ctl.sv:197:-      assign lsu_ld_data_r_shift[63:0] = lsu_rdata_r[63:0] >> 8*lsu_addr_r[1:0];
design/lsu/el2_lsu_dccm_ctl.sv:198:-      assign lsu_ld_data_r_nc[63:32]   = lsu_ld_data_r_shift[63:32];
design/lsu/el2_lsu_dccm_ctl.sv:199:-      assign lsu_ld_data_r[31:0]       = lsu_ld_data_r_shift[31:0];
design/lsu/el2_lsu_dccm_ctl.sv:200:-      assign {lsu_ld_data_corr_r_nc[63:32], lsu_ld_data_corr_r[31:0]} = lsu_rdata_corr_r[63:0] >> 8*lsu_addr_r[1:0];
design/lsu/el2_lsu_dccm_ctl.sv:201:-
design/lsu/el2_lsu_dccm_ctl.sv:202:-      assign picm_rd_data_r[63:32]   = picm_rd_data_r[31:0];
design/lsu/el2_lsu_dccm_ctl.sv:203:-      assign dccm_rdata_r[63:0]      = {dccm_

logic lsu_dccm_rden_d, lsu_dccm_wren_d;
logic ld_single_ecc_error_lo_r, ld_single_ecc_error_hi_r;
Expand Down Expand Up @@ -185,6 +185,7 @@
logic [3:0] stbuf_fwdbyteen_lo_r, stbuf_fwdbyteen_hi_r;
logic [31:0] lsu_rdata_lo_r, lsu_rdata_hi_r;
logic [63:0] picm_rd_data_r;
logic [63:0] lsu_ld_data_r_shift;
logic [63:32] lsu_ld_data_r_nc, lsu_ld_data_corr_r_nc;
logic [2:0] dma_mem_tag_r;
logic stbuf_fwddata_en;
Expand All @@ -193,7 +194,9 @@
assign dccm_dma_ecc_error = lsu_double_ecc_error_r;
assign dccm_dma_rtag[2:0] = dma_mem_tag_r[2:0];
assign dccm_dma_rdata[63:0] = ldst_dual_r ? lsu_rdata_corr_r[63:0] : {2{lsu_rdata_corr_r[31:0]}};
assign {lsu_ld_data_r_nc[63:32], lsu_ld_data_r[31:0]} = lsu_rdata_r[63:0] >> 8*lsu_addr_r[1:0];
assign lsu_ld_data_r_shift[63:0] = lsu_rdata_r[63:0] >> 8*lsu_addr_r[1:0];
assign lsu_ld_data_r_nc[63:32] = lsu_ld_data_r_shift[63:32];
assign lsu_ld_data_r[31:0] = lsu_ld_data_r_shift[31:0];
assign {lsu_ld_data_corr_r_nc[63:32], lsu_ld_data_corr_r[31:0]} = lsu_rdata_corr_r[63:0] >> 8*lsu_addr_r[1:0];

assign picm_rd_data_r[63:32] = picm_rd_data_r[31:0];
Expand Down
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