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Merge pull request #3748 from alainmarcel/alainmarcel-patch-1
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fix genblock name issue
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@alaindargelas
alaindargelas authored Jul 10, 2023
2 parents 422a18f + 488f3d4 commit 48c0ec4
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Showing 11 changed files with 1,503 additions and 1,557 deletions.
35 changes: 21 additions & 14 deletions src/DesignCompile/DesignElaboration.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -983,15 +983,7 @@ void DesignElaboration::elaborateInstance_(
VObjectType::slGenerate_module_named_block,
VObjectType::slGenerate_interface_named_block};

std::vector<NodeId> blockIds =
fC->sl_collect_all(subInstanceId, btypes, true);
if (!blockIds.empty()) {
NodeId blockId = blockIds[0];
NodeId blockNameId = fC->Child(blockId);
if (fC->Type(blockNameId) == VObjectType::slStringConst) {
modName = fC->SymName(blockNameId);
}
}
std::vector<NodeId> blockIds;
genBlkIndex++;
instName = modName;
std::string fullName;
Expand Down Expand Up @@ -1055,6 +1047,10 @@ void DesignElaboration::elaborateInstance_(
m_helper.checkForLoops(false);
bool cont = (validValue && (condVal > 0));

NodeId blockNameId = fC->Child(genBlock);
if (fC->Type(blockNameId) == VObjectType::slStringConst) {
modName = fC->SymName(blockNameId);
}
while (cont) {
Value* currentIndexValue = parent->getValue(name, m_exprBuilder);
uint64_t currVal = currentIndexValue->getValueUL();
Expand Down Expand Up @@ -1406,6 +1402,11 @@ void DesignElaboration::elaborateInstance_(
if (fC->Type(blockId) == VObjectType::slGenerate_begin_end_block &&
(fC->Type(fC->Child(blockId)) != VObjectType::slStringConst))
blockId = fC->Child(blockId);
NodeId blockNameId = fC->Child(blockId);
if (fC->Type(blockNameId) == VObjectType::slStringConst) {
modName = fC->SymName(blockNameId);
instName = modName;
}
std::string indexedModName = parent->getFullPathName() + "." + modName;
def = design->getComponentDefinition(indexedModName);
if (def == nullptr) {
Expand Down Expand Up @@ -2502,14 +2503,16 @@ void DesignElaboration::reduceUnnamedBlocks_() {
type == VObjectType::slLoop_generate_construct ||
type == VObjectType::slGenerate_module_loop_statement ||
type == VObjectType::slGenerate_interface_loop_statement ||
type == VObjectType::slGenerate_begin_end_block) &&
type == VObjectType::slGenerate_begin_end_block ||
type == VObjectType::slGenerate_item) &&
(typeP == VObjectType::slConditional_generate_construct ||
typeP == VObjectType::slGenerate_module_conditional_statement ||
typeP == VObjectType::slGenerate_interface_conditional_statement ||
typeP == VObjectType::slLoop_generate_construct ||
typeP == VObjectType::slGenerate_module_loop_statement ||
typeP == VObjectType::slGenerate_interface_loop_statement ||
typeP == VObjectType::slGenerate_region)) {
typeP == VObjectType::slGenerate_region ||
typeP == VObjectType::slGenerate_item)) {
std::string_view fullModName =
StringUtils::leaf(current->getModuleName());
std::string_view fullModNameP =
Expand All @@ -2522,9 +2525,13 @@ void DesignElaboration::reduceUnnamedBlocks_() {
parent->getParent()->overrideParentChild(parent->getParent(),
parent, current);
} else {
if (fullModNameP.find("genblk") != std::string::npos)
parent->getParent()->overrideParentChild(parent->getParent(),
parent, current);
if (type == VObjectType::slGenerate_item &&
typeP == VObjectType::slGenerate_item) {
} else {
if (fullModNameP.find("genblk") != std::string::npos)
parent->getParent()->overrideParentChild(parent->getParent(),
parent, current);
}
}
}
}
Expand Down
161 changes: 75 additions & 86 deletions tests/ExponTimeIfElseGen/ExponTimeIfElseGen.log
View file
Original file line number Diff line number Diff line change
Expand Up @@ -981,8 +981,8 @@ constant 273
design 1
event_control 1
gen_region 1
gen_scope 40
gen_scope_array 40
gen_scope 39
gen_scope_array 39
if_stmt 1
int_typespec 20
module_inst 5
Expand All @@ -1002,8 +1002,8 @@ constant 273
design 1
event_control 2
gen_region 1
gen_scope 60
gen_scope_array 60
gen_scope 58
gen_scope_array 58
if_stmt 2
int_typespec 20
module_inst 5
Expand Down Expand Up @@ -1140,113 +1140,102 @@ design: (work@Foo)
|vpiName:i
|vpiFullName:[email protected][1].i
|vpiGenScopeArray:
\_gen_scope_array: ([email protected][1].genblk1), line:14:18, endln:85:16
\_gen_scope_array: ([email protected][1].genblk1), line:15:17, endln:20:20
|vpiParent:
\_gen_scope: ([email protected][1]), line:5:45, endln:87:12
|vpiName:genblk1
|vpiFullName:[email protected][1].genblk1
|vpiGenScope:
\_gen_scope: ([email protected][1].genblk1), line:14:18, endln:85:16
\_gen_scope: ([email protected][1].genblk1), line:15:17, endln:20:20
|vpiParent:
\_gen_scope_array: ([email protected][1].genblk1), line:14:18, endln:85:16
\_gen_scope_array: ([email protected][1].genblk1), line:15:17, endln:20:20
|vpiFullName:[email protected][1].genblk1
|vpiGenScopeArray:
\_gen_scope_array: ([email protected][1].genblk1.genblk1), line:15:17, endln:20:20
|vpiProcess:
\_always: , line:15:17, endln:20:20
|vpiParent:
\_gen_scope: ([email protected][1].genblk1), line:14:18, endln:85:16
|vpiName:genblk1
|vpiFullName:[email protected][1].genblk1.genblk1
|vpiGenScope:
\_gen_scope: ([email protected][1].genblk1.genblk1), line:15:17, endln:20:20
\_gen_scope: ([email protected][1].genblk1), line:15:17, endln:20:20
|vpiStmt:
\_event_control: , line:15:27, endln:15:41
|vpiParent:
\_gen_scope_array: ([email protected][1].genblk1.genblk1), line:15:17, endln:20:20
|vpiFullName:[email protected][1].genblk1.genblk1
|vpiProcess:
\_always: , line:15:17, endln:20:20
|vpiCondition:
\_operation: , line:15:29, endln:15:40
|vpiParent:
\_gen_scope: ([email protected][1].genblk1.genblk1), line:15:17, endln:20:20
|vpiStmt:
\_event_control: , line:15:27, endln:15:41
|vpiOpType:39
|vpiOperand:
\_ref_obj: ([email protected][1].genblk1.clk), line:15:37, endln:15:40
|vpiParent:
\_always: , line:15:17, endln:20:20
|vpiCondition:
\_operation: , line:15:29, endln:15:40
|vpiName:clk
|vpiFullName:[email protected][1].genblk1.clk
|vpiStmt:
\_begin: ([email protected][1].genblk1), line:15:42, endln:20:20
|vpiParent:
\_event_control: , line:15:27, endln:15:41
|vpiFullName:[email protected][1].genblk1
|vpiStmt:
\_if_stmt: , line:16:21, endln:18:24
|vpiParent:
\_begin: ([email protected][1].genblk1), line:15:42, endln:20:20
|vpiCondition:
\_ref_obj: ([email protected][1].genblk1.shift_foo_bar), line:16:25, endln:16:38
|vpiParent:
\_event_control: , line:15:27, endln:15:41
|vpiOpType:39
|vpiOperand:
\_ref_obj: ([email protected][1].genblk1.genblk1.clk), line:15:37, endln:15:40
|vpiParent:
\_operation: , line:15:29, endln:15:40
|vpiName:clk
|vpiFullName:[email protected][1].genblk1.genblk1.clk
\_if_stmt: , line:16:21, endln:18:24
|vpiName:shift_foo_bar
|vpiFullName:[email protected][1].genblk1.shift_foo_bar
|vpiStmt:
\_begin: ([email protected][1].genblk1.genblk1), line:15:42, endln:20:20
\_begin: ([email protected][1].genblk1), line:16:41, endln:18:24
|vpiParent:
\_event_control: , line:15:27, endln:15:41
|vpiFullName:[email protected][1].genblk1.genblk1
|vpiStmt:
\_if_stmt: , line:16:21, endln:18:24
|vpiFullName:[email protected][1].genblk1
|vpiStmt:
\_assignment: , line:17:25, endln:17:55
|vpiParent:
\_begin: ([email protected][1].genblk1.genblk1), line:15:42, endln:20:20
|vpiCondition:
\_ref_obj: ([email protected][1].genblk1.genblk1.shift_foo_bar), line:16:25, endln:16:38
|vpiParent:
\_if_stmt: , line:16:21, endln:18:24
|vpiName:shift_foo_bar
|vpiFullName:[email protected][1].genblk1.genblk1.shift_foo_bar
|vpiStmt:
\_begin: ([email protected][1].genblk1.genblk1), line:16:41, endln:18:24
\_begin: ([email protected][1].genblk1), line:16:41, endln:18:24
|vpiOpType:82
|vpiRhs:
\_bit_select: ([email protected][1].genblk1.foo_bar_4), line:17:51, endln:17:54
|vpiParent:
\_if_stmt: , line:16:21, endln:18:24
|vpiFullName:[email protected][1].genblk1.genblk1
|vpiStmt:
\_assignment: , line:17:25, endln:17:55
|vpiName:foo_bar_4
|vpiFullName:[email protected][1].genblk1.foo_bar_4
|vpiIndex:
\_operation: , line:17:51, endln:17:54
|vpiParent:
\_begin: ([email protected][1].genblk1.genblk1), line:16:41, endln:18:24
|vpiOpType:82
|vpiRhs:
\_bit_select: ([email protected][1].genblk1.genblk1.foo_bar_4), line:17:51, endln:17:54
\_bit_select: ([email protected][1].genblk1.foo_bar_4), line:17:51, endln:17:54
|vpiOpType:24
|vpiOperand:
\_ref_obj: ([email protected][1].genblk1.foo_bar_4.i), line:17:51, endln:17:52
|vpiParent:
\_assignment: , line:17:25, endln:17:55
|vpiName:foo_bar_4
|vpiFullName:[email protected][1].genblk1.genblk1.foo_bar_4
|vpiIndex:
\_operation: , line:17:51, endln:17:54
|vpiParent:
\_bit_select: ([email protected][1].genblk1.genblk1.foo_bar_4), line:17:51, endln:17:54
|vpiOpType:24
|vpiOperand:
\_ref_obj: ([email protected][1].genblk1.genblk1.foo_bar_4.i), line:17:51, endln:17:52
|vpiParent:
\_operation: , line:17:51, endln:17:54
|vpiName:i
|vpiFullName:[email protected][1].genblk1.genblk1.foo_bar_4.i
|vpiActual:
\_parameter: ([email protected][1].i), line:5:0
|vpiOperand:
\_constant: , line:17:53, endln:17:54
|vpiParent:
\_operation: , line:17:51, endln:17:54
|vpiDecompile:1
|vpiSize:64
|UINT:1
|vpiConstType:9
|vpiLhs:
\_bit_select: ([email protected][1].genblk1.genblk1.foo_bar_4), line:17:25, endln:17:37
|vpiName:i
|vpiFullName:[email protected][1].genblk1.foo_bar_4.i
|vpiActual:
\_parameter: ([email protected][1].i), line:5:0
|vpiOperand:
\_constant: , line:17:53, endln:17:54
|vpiParent:
\_assignment: , line:17:25, endln:17:55
|vpiName:foo_bar_4
|vpiFullName:[email protected][1].genblk1.genblk1.foo_bar_4
|vpiIndex:
\_ref_obj: ([email protected][1].genblk1.genblk1.i), line:17:35, endln:17:36
|vpiParent:
\_bit_select: ([email protected][1].genblk1.genblk1.foo_bar_4), line:17:25, endln:17:37
|vpiName:i
|vpiFullName:[email protected][1].genblk1.genblk1.i
|vpiActual:
\_parameter: ([email protected][1].i), line:5:0
|vpiAlwaysType:3
\_operation: , line:17:51, endln:17:54
|vpiDecompile:1
|vpiSize:64
|UINT:1
|vpiConstType:9
|vpiLhs:
\_bit_select: ([email protected][1].genblk1.foo_bar_4), line:17:25, endln:17:37
|vpiParent:
\_assignment: , line:17:25, endln:17:55
|vpiName:foo_bar_4
|vpiFullName:[email protected][1].genblk1.foo_bar_4
|vpiIndex:
\_ref_obj: ([email protected][1].genblk1.i), line:17:35, endln:17:36
|vpiParent:
\_bit_select: ([email protected][1].genblk1.foo_bar_4), line:17:25, endln:17:37
|vpiName:i
|vpiFullName:[email protected][1].genblk1.i
|vpiActual:
\_parameter: ([email protected][1].i), line:5:0
|vpiAlwaysType:3
|vpiGenScopeArray:
\_gen_scope_array: ([email protected][2]), line:5:45, endln:87:12
|vpiParent:
Expand Down
28 changes: 14 additions & 14 deletions tests/GenBlock/GenBlock.log
View file
Original file line number Diff line number Diff line change
Expand Up @@ -136,12 +136,12 @@ AST_DEBUG_END

[INF:EL0526] Design Elaboration...

[INF:CP0335] ${SURELOG_DIR}/tests/GenBlock/dut.sv:18:9: Compile generate block "work@axi.ARRAY_INT".
[INF:CP0335] ${SURELOG_DIR}/tests/GenBlock/dut.sv:18:9: Compile generate block "work@axi.genblk1".

Instance tree:
[TOP] work@axi work@axi
[SCO] work@axi.ARRAY_INT work@axi.ARRAY_INT
[MOD] work@GOOD work@axi.ARRAY_INT.good
[SCO] work@axi.genblk1 work@axi.genblk1
[MOD] work@GOOD work@axi.genblk1.good

[NTE:EL0503] ${SURELOG_DIR}/tests/GenBlock/dut.sv:4:1: Top level module "work@axi".

Expand All @@ -155,9 +155,9 @@ Instance tree:

[NTE:EL0523] ${SURELOG_DIR}/tests/GenBlock/dut.sv:4:1: Instance "work@axi".

[NTE:EL0522] ${SURELOG_DIR}/tests/GenBlock/dut.sv:18:9: Scope "work@axi.ARRAY_INT".
[NTE:EL0522] ${SURELOG_DIR}/tests/GenBlock/dut.sv:18:9: Scope "work@axi.genblk1".

[NTE:EL0523] ${SURELOG_DIR}/tests/GenBlock/dut.sv:18:9: Instance "work@axi.ARRAY_INT.good".
[NTE:EL0523] ${SURELOG_DIR}/tests/GenBlock/dut.sv:18:9: Instance "work@axi.genblk1.good".

[INF:UH0706] Creating UHDM Model...

Expand Down Expand Up @@ -425,22 +425,22 @@ design: (work@axi)
|vpiTop:1
|vpiTopModule:1
|vpiGenScopeArray:
\_gen_scope_array: (work@axi.ARRAY_INT), line:18:9, endln:18:21
\_gen_scope_array: (work@axi.genblk1), line:18:9, endln:18:21
|vpiParent:
\_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10
|vpiName:ARRAY_INT
|vpiFullName:work@axi.ARRAY_INT
|vpiName:genblk1
|vpiFullName:work@axi.genblk1
|vpiGenScope:
\_gen_scope: (work@axi.ARRAY_INT), line:18:9, endln:18:21
\_gen_scope: (work@axi.genblk1), line:18:9, endln:18:21
|vpiParent:
\_gen_scope_array: (work@axi.ARRAY_INT), line:18:9, endln:18:21
|vpiFullName:work@axi.ARRAY_INT
\_gen_scope_array: (work@axi.genblk1), line:18:9, endln:18:21
|vpiFullName:work@axi.genblk1
|vpiModule:
\_module_inst: work@GOOD (work@axi.ARRAY_INT.good), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:18:9, endln:18:21
\_module_inst: work@GOOD (work@axi.genblk1.good), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:18:9, endln:18:21
|vpiParent:
\_gen_scope: (work@axi.ARRAY_INT), line:18:9, endln:18:21
\_gen_scope: (work@axi.genblk1), line:18:9, endln:18:21
|vpiName:good
|vpiFullName:work@axi.ARRAY_INT.good
|vpiFullName:work@axi.genblk1.good
|vpiDefName:work@GOOD
|vpiDefFile:${SURELOG_DIR}/tests/GenBlock/dut.sv
|vpiDefLineNo:1
Expand Down
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