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sequences, properties location #3961

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Feb 9, 2024
Merged

sequences, properties location #3961

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10 changes: 10 additions & 0 deletions src/DesignCompile/CompileAssertion.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -294,6 +294,7 @@ UHDM::any* CompileHelper::compileSimpleImmediateAssertion(
switch (fC->Type(the_stmt)) {
case VObjectType::paSimple_immediate_assert_statement: {
UHDM::immediate_assert* astmt = s.MakeImmediate_assert();
fC->populateCoreMembers(the_stmt, the_stmt, astmt);
astmt->VpiParent(pstmt);
astmt->Expr((UHDM::expr*)expr);
if (expr) expr->VpiParent(astmt);
Expand All @@ -306,6 +307,7 @@ UHDM::any* CompileHelper::compileSimpleImmediateAssertion(
}
case VObjectType::paSimple_immediate_assume_statement: {
UHDM::immediate_assume* astmt = s.MakeImmediate_assume();
fC->populateCoreMembers(the_stmt, the_stmt, astmt);
astmt->VpiParent(pstmt);
astmt->Expr((UHDM::expr*)expr);
if (expr) expr->VpiParent(astmt);
Expand All @@ -318,6 +320,7 @@ UHDM::any* CompileHelper::compileSimpleImmediateAssertion(
}
case VObjectType::paSimple_immediate_cover_statement: {
UHDM::immediate_cover* astmt = s.MakeImmediate_cover();
fC->populateCoreMembers(the_stmt, the_stmt, astmt);
astmt->VpiParent(pstmt);
astmt->Expr((UHDM::expr*)expr);
if (expr) expr->VpiParent(astmt);
Expand Down Expand Up @@ -385,6 +388,7 @@ UHDM::any* CompileHelper::compileDeferredImmediateAssertion(
switch (fC->Type(the_stmt)) {
case VObjectType::paDeferred_immediate_assert_statement: {
UHDM::immediate_assert* astmt = s.MakeImmediate_assert();
fC->populateCoreMembers(the_stmt, the_stmt, astmt);
astmt->VpiParent(pstmt);
astmt->Expr((UHDM::expr*)expr);
if (expr) expr->VpiParent(astmt);
Expand All @@ -399,6 +403,7 @@ UHDM::any* CompileHelper::compileDeferredImmediateAssertion(
}
case VObjectType::paDeferred_immediate_assume_statement: {
UHDM::immediate_assume* astmt = s.MakeImmediate_assume();
fC->populateCoreMembers(the_stmt, the_stmt, astmt);
astmt->VpiParent(pstmt);
astmt->Expr((UHDM::expr*)expr);
if (expr) expr->VpiParent(astmt);
Expand All @@ -413,6 +418,7 @@ UHDM::any* CompileHelper::compileDeferredImmediateAssertion(
}
case VObjectType::paDeferred_immediate_cover_statement: {
UHDM::immediate_cover* astmt = s.MakeImmediate_cover();
fC->populateCoreMembers(the_stmt, the_stmt, astmt);
astmt->VpiParent(pstmt);
astmt->Expr((UHDM::expr*)expr);
if (expr) expr->VpiParent(astmt);
Expand All @@ -435,6 +441,7 @@ UHDM::property_decl* CompileHelper::compilePropertyDeclaration(
ValuedComponentI* instance) {
UHDM::Serializer& s = compileDesign->getSerializer();
UHDM::property_decl* result = s.MakeProperty_decl();
fC->populateCoreMembers(nodeId, nodeId, result);
std::string_view propName = fC->SymName(nodeId);
result->VpiName(propName);
result->VpiParent(pstmt);
Expand Down Expand Up @@ -518,6 +525,7 @@ UHDM::sequence_decl* CompileHelper::compileSequenceDeclaration(
ValuedComponentI* instance) {
UHDM::Serializer& s = compileDesign->getSerializer();
UHDM::sequence_decl* result = s.MakeSequence_decl();
fC->populateCoreMembers(nodeId, nodeId, result);
std::string_view propName = fC->SymName(nodeId);
result->VpiName(propName);
result->VpiParent(pstmt);
Expand All @@ -537,6 +545,7 @@ UHDM::sequence_decl* CompileHelper::compileSequenceDeclaration(

NodeId Port_name = fC->Sibling(Sequence_formal_type);
UHDM::seq_formal_decl* prop_port_decl = s.MakeSeq_formal_decl();
fC->populateCoreMembers(Sequence_expr, Sequence_expr, prop_port_decl);
ports->push_back(prop_port_decl);
prop_port_decl->VpiName(fC->SymName(Port_name));
UHDM::ref_typespec* rtps = s.MakeRef_typespec();
Expand All @@ -549,6 +558,7 @@ UHDM::sequence_decl* CompileHelper::compileSequenceDeclaration(
NodeId lookup = fC->Child(Sequence_expr);
if (fC->Type(lookup) == VObjectType::paClocking_event) {
UHDM::multiclock_sequence_expr* mexpr = s.MakeMulticlock_sequence_expr();
fC->populateCoreMembers(Sequence_expr, Sequence_expr, mexpr);
result->Sequence_expr_multiclock_group(mexpr);
mexpr->Clocked_seqs(s.MakeClocked_seqVec());
while (fC->Type(lookup) == VObjectType::paClocking_event) {
Expand Down
1 change: 1 addition & 0 deletions src/DesignCompile/CompileExpression.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2245,6 +2245,7 @@ UHDM::any *CompileHelper::compileExpression(
NodeId NameId = fC->Child(Ps_or_hierarchical_array_identifier);
const std::string_view name = fC->SymName(NameId);
sequence_inst *seqinst = s.MakeSequence_inst();
fC->populateCoreMembers(child, child, seqinst);
seqinst->VpiName(name);
seqinst->VpiParent(pexpr);
NodeId Sequence_list_of_arguments =
Expand Down
81 changes: 52 additions & 29 deletions tests/AssertDelayError/AssertDelayError.log
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54 changes: 34 additions & 20 deletions tests/AssertTempError/AssertTempError.log
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Original file line number Diff line number Diff line change
Expand Up @@ -2804,15 +2804,15 @@ design: (work@tb_UART)
\_design: (work@tb_UART)
|vpiFullName:work@UART_assertions
|vpiPropertyDecl:
\_property_decl: (work@tb_UART.uart_inst.uut.p_send)
\_property_decl: (work@tb_UART.uart_inst.uut.p_send), line:82:14, endln:82:20
|vpiParent:
\_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80
|vpiName:p_send
|vpiFullName:work@tb_UART.uart_inst.uut.p_send
|vpiPropertySpec:
\_property_spec: , line:83:9, endln:84:33
|vpiParent:
\_property_decl: (work@tb_UART.uart_inst.uut.p_send)
\_property_decl: (work@tb_UART.uart_inst.uut.p_send), line:82:14, endln:82:20
|vpiClockingEvent:
\_operation: , line:83:11, endln:83:22
|vpiParent:
Expand Down Expand Up @@ -2861,15 +2861,15 @@ design: (work@tb_UART)
|vpiActual:
\_parameter: (work@tb_UART.uart_inst.uut.DATA), line:79:36, endln:79:40
|vpiPropertyDecl:
\_property_decl: (work@tb_UART.uart_inst.uut.p_done)
\_property_decl: (work@tb_UART.uart_inst.uut.p_done), line:90:14, endln:90:20
|vpiParent:
\_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80
|vpiName:p_done
|vpiFullName:work@tb_UART.uart_inst.uut.p_done
|vpiPropertySpec:
\_property_spec: , line:91:9, endln:92:33
|vpiParent:
\_property_decl: (work@tb_UART.uart_inst.uut.p_done)
\_property_decl: (work@tb_UART.uart_inst.uut.p_done), line:90:14, endln:90:20
|vpiClockingEvent:
\_operation: , line:91:11, endln:91:22
|vpiParent:
Expand Down Expand Up @@ -3125,7 +3125,7 @@ design: (work@tb_UART)
|vpiName:p_send
|vpiFullName:work@tb_UART.uart_inst.uut.p_send
|vpiActual:
\_property_decl: (work@tb_UART.uart_inst.uut.p_send)
\_property_decl: (work@tb_UART.uart_inst.uut.p_send), line:82:14, endln:82:20
|vpiAssertion:
\_assert_stmt: (work@tb_UART.uart_inst.uut), line:95:5, endln:95:70
|vpiParent:
Expand Down Expand Up @@ -3155,7 +3155,7 @@ design: (work@tb_UART)
|vpiName:p_done
|vpiFullName:work@tb_UART.uart_inst.uut.p_done
|vpiActual:
\_property_decl: (work@tb_UART.uart_inst.uut.p_done)
\_property_decl: (work@tb_UART.uart_inst.uut.p_done), line:90:14, endln:90:20
|vpiPort:
\_port: (clk), line:71:11, endln:71:14
|vpiParent:
Expand Down Expand Up @@ -5478,15 +5478,15 @@ design: (work@tb_UART)
|vpiName:uut
|vpiFullName:work@tb_UART.uut
|vpiPropertyDecl:
\_property_decl: (work@tb_UART.uart_inst.uut.p_send)
\_property_decl: (work@tb_UART.uart_inst.uut.p_send), line:82:14, endln:82:20
|vpiParent:
\_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80
|vpiName:p_send
|vpiFullName:work@tb_UART.uart_inst.uut.p_send
|vpiPropertySpec:
\_property_spec: , line:83:9, endln:84:33
|vpiParent:
\_property_decl: (work@tb_UART.uart_inst.uut.p_send)
\_property_decl: (work@tb_UART.uart_inst.uut.p_send), line:82:14, endln:82:20
|vpiClockingEvent:
\_operation: , line:83:11, endln:83:22
|vpiParent:
Expand Down Expand Up @@ -5535,15 +5535,15 @@ design: (work@tb_UART)
|vpiActual:
\_parameter: (work@tb_UART.uart_inst.uut.DATA), line:79:36, endln:79:40
|vpiPropertyDecl:
\_property_decl: (work@tb_UART.uart_inst.uut.p_done)
\_property_decl: (work@tb_UART.uart_inst.uut.p_done), line:90:14, endln:90:20
|vpiParent:
\_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80
|vpiName:p_done
|vpiFullName:work@tb_UART.uart_inst.uut.p_done
|vpiPropertySpec:
\_property_spec: , line:91:9, endln:92:33
|vpiParent:
\_property_decl: (work@tb_UART.uart_inst.uut.p_done)
\_property_decl: (work@tb_UART.uart_inst.uut.p_done), line:90:14, endln:90:20
|vpiClockingEvent:
\_operation: , line:91:11, endln:91:22
|vpiParent:
Expand Down Expand Up @@ -5823,7 +5823,7 @@ design: (work@tb_UART)
|vpiName:p_send
|vpiFullName:work@tb_UART.uart_inst.uut.p_send
|vpiActual:
\_property_decl: (work@tb_UART.uart_inst.uut.p_send)
\_property_decl: (work@tb_UART.uart_inst.uut.p_send), line:82:14, endln:82:20
|vpiAssertion:
\_assert_stmt: (work@tb_UART.uart_inst.uut), line:95:5, endln:95:70
|vpiParent:
Expand All @@ -5847,7 +5847,7 @@ design: (work@tb_UART)
|vpiName:p_done
|vpiFullName:work@tb_UART.uart_inst.uut.p_done
|vpiActual:
\_property_decl: (work@tb_UART.uart_inst.uut.p_done)
\_property_decl: (work@tb_UART.uart_inst.uut.p_done), line:90:14, endln:90:20
|vpiInstance:
\_module_inst: work@UART (work@tb_UART.uart_inst), file:${SURELOG_DIR}/tests/AssertTempError/testbench.sv, line:10:5, endln:18:7
|vpiPort:
Expand Down Expand Up @@ -5981,15 +5981,15 @@ design: (work@tb_UART)
|vpiName:uut
|vpiFullName:work@tb_UART.uut
|vpiPropertyDecl:
\_property_decl: (work@tb_UART.uart_inst.uut.p_send)
\_property_decl: (work@tb_UART.uart_inst.uut.p_send), line:82:14, endln:82:20
|vpiParent:
\_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80
|vpiName:p_send
|vpiFullName:work@tb_UART.uart_inst.uut.p_send
|vpiPropertySpec:
\_property_spec: , line:83:9, endln:84:33
|vpiParent:
\_property_decl: (work@tb_UART.uart_inst.uut.p_send)
\_property_decl: (work@tb_UART.uart_inst.uut.p_send), line:82:14, endln:82:20
|vpiClockingEvent:
\_operation: , line:83:11, endln:83:22
|vpiParent:
Expand Down Expand Up @@ -6038,15 +6038,15 @@ design: (work@tb_UART)
|vpiActual:
\_parameter: (work@tb_UART.uart_inst.uut.DATA), line:79:36, endln:79:40
|vpiPropertyDecl:
\_property_decl: (work@tb_UART.uart_inst.uut.p_done)
\_property_decl: (work@tb_UART.uart_inst.uut.p_done), line:90:14, endln:90:20
|vpiParent:
\_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80
|vpiName:p_done
|vpiFullName:work@tb_UART.uart_inst.uut.p_done
|vpiPropertySpec:
\_property_spec: , line:91:9, endln:92:33
|vpiParent:
\_property_decl: (work@tb_UART.uart_inst.uut.p_done)
\_property_decl: (work@tb_UART.uart_inst.uut.p_done), line:90:14, endln:90:20
|vpiClockingEvent:
\_operation: , line:91:11, endln:91:22
|vpiParent:
Expand Down Expand Up @@ -6326,7 +6326,7 @@ design: (work@tb_UART)
|vpiName:p_send
|vpiFullName:work@tb_UART.uart_inst.uut.p_send
|vpiActual:
\_property_decl: (work@tb_UART.uart_inst.uut.p_send)
\_property_decl: (work@tb_UART.uart_inst.uut.p_send), line:82:14, endln:82:20
|vpiAssertion:
\_assert_stmt: (work@tb_UART.uart_inst.uut), line:95:5, endln:95:70
|vpiParent:
Expand All @@ -6350,7 +6350,7 @@ design: (work@tb_UART)
|vpiName:p_done
|vpiFullName:work@tb_UART.uart_inst.uut.p_done
|vpiActual:
\_property_decl: (work@tb_UART.uart_inst.uut.p_done)
\_property_decl: (work@tb_UART.uart_inst.uut.p_done), line:90:14, endln:90:20
|vpiInstance:
\_module_inst: work@UART (work@tb_UART.uart_inst), file:${SURELOG_DIR}/tests/AssertTempError/testbench.sv, line:10:5, endln:18:7
|vpiPort:
Expand Down Expand Up @@ -6945,7 +6945,11 @@ design: (work@tb_UART)

============================== Begin Linting Results ==============================
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:83:9: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:100:11: Non synthesizable construct, uut
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:82:14: Non synthesizable construct, p_send
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:91:9: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:90:14: Non synthesizable construct, p_done
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:87:21: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:95:22: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/testbench.sv:23:9: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/testbench.sv:37:9: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/testbench.sv:38:9: Non synthesizable construct,
Expand All @@ -6959,5 +6963,15 @@ design: (work@tb_UART)
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/testbench.sv:46:13: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/testbench.sv:48:13: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:83:9: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:100:11: Non synthesizable construct, uut
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:82:14: Non synthesizable construct, p_send
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:91:9: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:90:14: Non synthesizable construct, p_done
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:87:21: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:95:22: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:83:9: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:82:14: Non synthesizable construct, p_send
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:91:9: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:90:14: Non synthesizable construct, p_done
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:87:21: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:95:22: Non synthesizable construct,
============================== End Linting Results ==============================
17 changes: 10 additions & 7 deletions tests/Assertions/Assertions.log
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Original file line number Diff line number Diff line change
Expand Up @@ -506,7 +506,7 @@ design: (work@m)
\_design: (work@m)
|vpiFullName:work@m
|vpiPropertyDecl:
\_property_decl: ([email protected])
\_property_decl: ([email protected]), line:9:10, endln:9:17
|vpiParent:
\_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14
|vpiName:toggles
Expand All @@ -526,7 +526,7 @@ design: (work@m)
|vpiPropertySpec:
\_property_spec: , line:10:1, endln:10:58
|vpiParent:
\_property_decl: ([email protected])
\_property_decl: ([email protected]), line:9:10, endln:9:17
|vpiPropertyExpr:
\_operation: , line:10:1, endln:10:58
|vpiParent:
Expand Down Expand Up @@ -835,15 +835,15 @@ design: (work@m)
\_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14
|vpiName:work@m
|vpiPropertyDecl:
\_property_decl: ([email protected])
\_property_decl: ([email protected]), line:9:10, endln:9:17
|vpiParent:
\_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14
|vpiName:toggles
|vpiFullName:[email protected]
|vpiPropFormalDecl:
\_prop_formal_decl: (x)
|vpiParent:
\_property_decl: ([email protected])
\_property_decl: ([email protected]), line:9:10, endln:9:17
|vpiName:x
|vpiTypespec:
\_ref_typespec: ([email protected])
Expand All @@ -855,7 +855,7 @@ design: (work@m)
|vpiPropFormalDecl:
\_prop_formal_decl: (y)
|vpiParent:
\_property_decl: ([email protected])
\_property_decl: ([email protected]), line:9:10, endln:9:17
|vpiName:y
|vpiTypespec:
\_ref_typespec: ([email protected])
Expand All @@ -865,7 +865,7 @@ design: (work@m)
|vpiPropertySpec:
\_property_spec: , line:10:1, endln:10:58
|vpiParent:
\_property_decl: ([email protected])
\_property_decl: ([email protected]), line:9:10, endln:9:17
|vpiPropertyExpr:
\_operation: , line:10:1, endln:10:58
|vpiParent:
Expand Down Expand Up @@ -1289,5 +1289,8 @@ design: (work@m)

============================== Begin Linting Results ==============================
[LINT]: ${SURELOG_DIR}/tests/Assertions/dut.sv:10:1: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/Assertions/dut.sv:1:1: Non synthesizable construct, work@m
[LINT]: ${SURELOG_DIR}/tests/Assertions/dut.sv:9:10: Non synthesizable construct, toggles
[LINT]: ${SURELOG_DIR}/tests/Assertions/dut.sv:12:22: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/tests/Assertions/dut.sv:9:10: Non synthesizable construct, toggles
[LINT]: ${SURELOG_DIR}/tests/Assertions/dut.sv:12:22: Non synthesizable construct,
============================== End Linting Results ==============================
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