Add ID signal to component interface

chipsalliance · Jul 25, 2024 · 29bedff · 29bedff
1 parent 53536e0
commit 29bedff
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Showing 4 changed files with 16 additions and 0 deletions.
diff --git a/src/axi/rtl/axi_sub.sv b/src/axi/rtl/axi_sub.sv
@@ -53,6 +53,7 @@ module axi_sub import axi_pkg::*; #(
     output logic          dv,
     output logic [AW-1:0] addr, // Byte address
     output logic [UW-1:0] user,
+    output logic [IW-1:0] id,
     output logic [DW-1:0] wdata, // Requires: Component dwidth == AXI dwidth
     output logic [BC-1:0] wstrb, // Requires: Component dwidth == AXI dwidth
     input  logic [DW-1:0] rdata, // Requires: Component dwidth == AXI dwidth
@@ -71,6 +72,7 @@ module axi_sub import axi_pkg::*; #(
     logic          r_dv;
     logic [AW-1:0] r_addr;  // Byte address
     logic [UW-1:0] r_user;
+    logic [IW-1:0] r_id;
     logic          r_last;  // Asserted with final 'dv' of a burst
     logic          r_hld;
     logic          r_err;
@@ -81,6 +83,7 @@ module axi_sub import axi_pkg::*; #(
     logic          w_dv;
     logic [AW-1:0] w_addr;  // Byte address
     logic [UW-1:0] w_user;
+    logic [IW-1:0] w_id;
     logic [DW-1:0] w_wdata; // Requires: Component dwidth == AXI dwidth
     logic [BC-1:0] w_wstrb; // Requires: Component dwidth == AXI dwidth
     logic          w_last;  // Asserted with final 'dv' of a burst
@@ -111,6 +114,7 @@ module axi_sub import axi_pkg::*; #(
         .dv   (w_dv   ),
         .addr (w_addr ),
         .user (w_user ),
+        .id   (w_id   ),
         .wdata(w_wdata),
         .wstrb(w_wstrb),
         .last (w_last ),
@@ -143,6 +147,7 @@ module axi_sub import axi_pkg::*; #(
         .dv   (r_dv   ),
         .addr (r_addr ),
         .user (r_user ),
+        .id   (r_id   ),
         .last (r_last ),
         .hld  (r_hld  ),
         .err  (r_err  ),
@@ -166,6 +171,7 @@ module axi_sub import axi_pkg::*; #(
         .r_dv   (r_dv   ),
         .r_addr (r_addr ),
         .r_user (r_user ),
+        .r_id   (r_id   ),
         .r_last (r_last ),
         .r_hld  (r_hld  ),
         .r_err  (r_err  ),
@@ -175,6 +181,7 @@ module axi_sub import axi_pkg::*; #(
         .w_dv   (w_dv   ),
         .w_addr (w_addr ),
         .w_user (w_user ),
+        .w_id   (w_id   ),
         .w_wdata(w_wdata),
         .w_wstrb(w_wstrb),
         .w_last (w_last ),
@@ -185,6 +192,7 @@ module axi_sub import axi_pkg::*; #(
         .dv     (dv     ),
         .addr   (addr   ),
         .user   (user   ),
+        .id     (id     ),
         .wdata  (wdata  ),
         .wstrb  (wstrb  ),
         .last   (last   ),

diff --git a/src/axi/rtl/axi_sub_arb.sv b/src/axi/rtl/axi_sub_arb.sv
@@ -44,6 +44,7 @@ module axi_sub_arb import axi_pkg::*; #(
     input  logic          r_dv,
     input  logic [AW-1:0] r_addr,  // Byte address
     input  logic [UW-1:0] r_user,
+    input  logic [IW-1:0] r_id,
     input  logic          r_last,  // Asserted with final 'dv' of a burst
     output logic          r_hld,
     output logic          r_err,
@@ -54,6 +55,7 @@ module axi_sub_arb import axi_pkg::*; #(
     input  logic          w_dv,
     input  logic [AW-1:0] w_addr,  // Byte address
     input  logic [UW-1:0] w_user,
+    input  logic [IW-1:0] w_id,
     input  logic [DW-1:0] w_wdata, // Requires: Component dwidth == AXI dwidth
     input  logic [BC-1:0] w_wstrb, // Requires: Component dwidth == AXI dwidth
     input  logic          w_last,  // Asserted with final 'dv' of a burst
@@ -64,6 +66,7 @@ module axi_sub_arb import axi_pkg::*; #(
     output logic          dv,
     output logic [AW-1:0] addr, // Byte address
     output logic [UW-1:0] user,
+    output logic [IW-1:0] id,
     output logic [DW-1:0] wdata, // Requires: Component dwidth == AXI dwidth
     output logic [BC-1:0] wstrb, // Requires: Component dwidth == AXI dwidth
     output logic          last, // Asserted with final 'dv' of a burst
@@ -116,6 +119,7 @@ module axi_sub_arb import axi_pkg::*; #(
         dv      = r_dv || w_dv;
         addr    = r_win ? r_addr : w_addr;
         user    = r_win ? r_user : w_user;
+        id      = r_win ? r_id   : w_id  ;
         last    = r_win ? r_last : w_last;
         r_hld   = hld || !r_win;
         w_hld   = hld ||  r_win;

diff --git a/src/axi/rtl/axi_sub_rd.sv b/src/axi/rtl/axi_sub_rd.sv
@@ -55,6 +55,7 @@ module axi_sub_rd import axi_pkg::*; #(
     output logic          dv,
     output logic [AW-1:0] addr, // Byte address
     output logic [UW-1:0] user,
+    output logic [IW-1:0] id,
     output logic          last, // Asserted with final 'dv' of a burst
     input  logic          hld,
     input  logic          err,
@@ -165,6 +166,7 @@ module axi_sub_rd import axi_pkg::*; #(
     // Force aligned address to component
     always_comb addr = {txn_ctx.addr[AW-1:BW],BW'(0)};
     always_comb user = txn_ctx.user;
+    always_comb id   = txn_ctx.id;
 
     // Use full address to calculate next address (in case of arsize < data width)
     axi_addr #(

diff --git a/src/axi/rtl/axi_sub_wr.sv b/src/axi/rtl/axi_sub_wr.sv
@@ -51,6 +51,7 @@ module axi_sub_wr import axi_pkg::*; #(
     output logic          dv,
     output logic [AW-1:0] addr, // Byte address
     output logic [UW-1:0] user,
+    output logic [IW-1:0] id,
     output logic [DW-1:0] wdata, // Requires: Component dwidth == AXI dwidth
     output logic [BC-1:0] wstrb, // Requires: Component dwidth == AXI dwidth
     output logic          last, // Asserted with final 'dv' of a burst
@@ -198,6 +199,7 @@ module axi_sub_wr import axi_pkg::*; #(
     // Force aligned address to component
     always_comb addr = {txn_ctx.addr[AW-1:BW],BW'(0)};
     always_comb user = txn_ctx.user;
+    always_comb id   = txn_ctx.id;
 
     // Use full address to calculate next address (in case of AxSIZE < data width)
     axi_addr #(