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Issue 445 LINT fixes
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Matthew Border committed Mar 1, 2024
1 parent bbc9a32 commit 33d49ab
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Showing 28 changed files with 370 additions and 256 deletions.
24 changes: 13 additions & 11 deletions src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
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Expand Up @@ -25,17 +25,19 @@ package caliptra_prim_util_pkg;
* vector value. The argument shall be treated as an unsigned
* value, and an argument value of 0 shall produce a result of 0.
*/
function automatic integer _clog2(integer value);
integer result;
// Use an intermediate value to avoid assigning to an input port, which produces a warning in
// Synopsys DC.
integer v = value;
v = v - 1;
for (result = 0; v > 0; result++) begin
v = v >> 1;
end
return result;
endfunction

//Function causing LINT errors. Not used in current codebase
//deprecated and replaced by $clog2() //function automatic integer _clog2(integer value);
//deprecated and replaced by $clog2() // integer result;
//deprecated and replaced by $clog2() // Use an intermediate value to avoid assigning to an input port, which produces a warning in
//deprecated and replaced by $clog2() // Synopsys DC.
//deprecated and replaced by $clog2() // integer v = value;
//deprecated and replaced by $clog2() // v = v - 1;
//deprecated and replaced by $clog2() // for (result = 0; v > 0; result++) begin
//deprecated and replaced by $clog2() // v = v >> 1;
//deprecated and replaced by $clog2() // end
//deprecated and replaced by $clog2() // return result;
//deprecated and replaced by $clog2() //endfunction


/**
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2 changes: 1 addition & 1 deletion src/doe/rtl/doe_fsm.sv
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Expand Up @@ -147,7 +147,7 @@ always_comb begin : kv_doe_fsm
dest_write_offset_nxt = dest_write_offset;
flow_done = '0;

unique casez (kv_doe_fsm_ps)
unique case (kv_doe_fsm_ps)
DOE_IDLE: begin
if (arc_DOE_IDLE_DOE_INIT) kv_doe_fsm_ns = DOE_INIT;
//assert flow done if a locked flow is attempted
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10 changes: 5 additions & 5 deletions src/ecc/rtl/ecc_dsa_ctrl.sv
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Expand Up @@ -536,7 +536,7 @@ module ecc_dsa_ctrl
hw_verify_r_we = 0;
hw_pk_chk_we = 0;
if ((prog_instr.opcode == DSA_UOP_RD_CORE) & (cycle_cnt == 0)) begin
unique casez (prog_instr.reg_id)
unique case (prog_instr.reg_id)
PRIVKEY_ID : hw_privkey_we = 1;
PUBKEYX_ID : hw_pubkeyx_we = 1;
PUBKEYY_ID : hw_pubkeyy_we = 1;
Expand Down Expand Up @@ -569,7 +569,7 @@ module ecc_dsa_ctrl
begin : write_to_pm_core
write_reg = '0;
if (prog_instr.opcode == DSA_UOP_WR_CORE) begin
unique casez (prog_instr.reg_id)
unique case (prog_instr.reg_id)
CONST_ZERO_ID : write_reg = {zero_pad, ZERO_CONST};
CONST_ONE_ID : write_reg = {zero_pad, ONE_CONST};
CONST_E_a_MONT_ID : write_reg = {zero_pad, E_a_MONT};
Expand All @@ -594,7 +594,7 @@ module ecc_dsa_ctrl
endcase
end
else if (prog_instr.opcode == DSA_UOP_WR_SCALAR) begin
unique casez (prog_instr.reg_id)
unique case (prog_instr.reg_id)
SCALAR_PK_ID : write_reg = (scalar_PK_reg << RND_SIZE);
SCALAR_G_ID : write_reg = (scalar_G_reg << RND_SIZE);
SCALAR_ID : write_reg = scalar_out_reg; // SCA
Expand Down Expand Up @@ -727,13 +727,13 @@ module ecc_dsa_ctrl
end
else begin
cycle_cnt <= '0;
unique casez (prog_cntr)
unique case (prog_cntr)
DSA_NOP : begin
keygen_process <= 0;
signing_process <= 0;
verifying_process <= 0;
// Waiting for new valid command
unique casez (cmd_reg)
unique case (cmd_reg)
KEYGEN : begin // keygen
prog_cntr <= DSA_KG_S;
dsa_valid_reg <= 0;
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2 changes: 1 addition & 1 deletion src/ecc/rtl/ecc_dsa_sequencer.sv
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Expand Up @@ -64,7 +64,7 @@ module ecc_dsa_sequencer
end
else begin
if (ena) begin
unique casez(addra)
unique case(addra)
//PM CORE INIT
0 : douta <= {DSA_UOP_NOP, NOP_ID, UOP_OPR_DONTCARE};
1 : douta <= {DSA_UOP_WR_CORE, CONST_ZERO_ID, UOP_OPR_CONST_ZERO};
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6 changes: 3 additions & 3 deletions src/ecc/rtl/ecc_dsa_uop_pkg.sv
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Expand Up @@ -105,8 +105,8 @@ localparam [DSA_OPR_ADDR_WIDTH-1 : 0] MASKING_ID = 6'd28;
localparam [DSA_OPR_ADDR_WIDTH-1 : 0] PK_VALID_ID = 6'd29;

// DSA Subroutine listing
localparam [DSA_PROG_ADDR_W-1 : 0] DSA_RESET = 6'd0;
localparam [DSA_PROG_ADDR_W-1 : 0] DSA_NOP = 6'd12;
localparam [DSA_PROG_ADDR_W-1 : 0] DSA_RESET = 7'd0;
localparam [DSA_PROG_ADDR_W-1 : 0] DSA_NOP = 7'd12;
localparam [DSA_PROG_ADDR_W-1 : 0] DSA_KG_S = DSA_NOP + 2;
localparam [DSA_PROG_ADDR_W-1 : 0] DSA_KG_E = DSA_KG_S + 12;
localparam [DSA_PROG_ADDR_W-1 : 0] DSA_SGN_S = DSA_KG_E + 2;
Expand All @@ -117,4 +117,4 @@ localparam [DSA_PROG_ADDR_W-1 : 0] DSA_VER_E = DSA_VER_S + 23

endpackage

`endif
`endif
8 changes: 4 additions & 4 deletions src/ecc/rtl/ecc_hmac_drbg_interface.sv
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Expand Up @@ -140,7 +140,7 @@ module ecc_hmac_drbg_interface#(

always_comb
begin : hmac_drbg_entropy_input
unique casez (state_reg)
unique case (state_reg)
LFSR_ST: hmac_drbg_entropy = IV;
LAMBDA_ST: hmac_drbg_entropy = IV;
SCALAR_RND_ST: hmac_drbg_entropy = IV;
Expand All @@ -153,7 +153,7 @@ module ecc_hmac_drbg_interface#(

always_comb
begin : hmac_drbg_nonce_input
unique casez (state_reg)
unique case (state_reg)
LFSR_ST: hmac_drbg_nonce = counter_nonce_reg;
LAMBDA_ST: hmac_drbg_nonce = counter_nonce_reg;
SCALAR_RND_ST: hmac_drbg_nonce = counter_nonce_reg;
Expand All @@ -171,7 +171,7 @@ module ecc_hmac_drbg_interface#(
hmac_drbg_init = 0;
hmac_drbg_next = 0;
if (first_round) begin
unique casez (state_reg)
unique case (state_reg)
LFSR_ST: hmac_drbg_init = 1;
LAMBDA_ST: hmac_drbg_next = 1;
SCALAR_RND_ST: hmac_drbg_next = 1;
Expand Down Expand Up @@ -291,7 +291,7 @@ module ecc_hmac_drbg_interface#(
always_comb
begin : interface_fsm
state_next = IDLE_ST;
unique casez(state_reg)
unique case(state_reg)
IDLE_ST: state_next = (en & hmac_drbg_ready)? LFSR_ST : IDLE_ST;
LFSR_ST: state_next = (hmac_done_edge)? LAMBDA_ST : LFSR_ST;
LAMBDA_ST: state_next = (hmac_done_edge)? SCALAR_RND_ST : LAMBDA_ST;
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14 changes: 7 additions & 7 deletions src/ecc/rtl/ecc_pm_ctrl.sv
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Expand Up @@ -150,7 +150,7 @@ module ecc_pm_ctrl
stall_cntr <= stall_cntr - 1;
end
else if (stall_flag & (!stalled) & (!stalled_pipe1)) begin
unique casez (prog_instr.opcode)
unique case (prog_instr.opcode)
UOP_DO_ADD_p : begin stalled <= 1'b1; stall_cntr <= ADD_DELAY; end // ADD
UOP_DO_SUB_p : begin stalled <= 1'b1; stall_cntr <= ADD_DELAY; end // SUB
UOP_DO_MUL_p : begin stalled <= 1'b1; stall_cntr <= MULT_DELAY; end // MULT
Expand All @@ -162,10 +162,10 @@ module ecc_pm_ctrl
end
else if ((!stalled) | (stalled & (stall_cntr == 0))) begin
stalled <= 0;
unique casez (prog_cntr)
unique case (prog_cntr)
NOP : begin // Waiting for new valid command
ecc_cmd_reg <= ecc_cmd_i;
unique casez (ecc_cmd_i)
unique case (ecc_cmd_i)
KEYGEN_CMD : begin // keygen
mont_cntr <= (sca_en_i)? Secp384_SCA_MONT_COUNT : Secp384_MONT_COUNT;
prog_cntr <= PM_INIT_G_S;
Expand Down Expand Up @@ -231,7 +231,7 @@ module ecc_pm_ctrl

PD_E : begin //End of point doubling
if (mont_cntr == 0) begin // Montgomery ladder is done
unique casez (ecc_cmd_reg)
unique case (ecc_cmd_reg)
VER_PART1_CMD : prog_cntr <= NOP;
VER_PART2_CMD : prog_cntr <= VER2_PA_S;
default : prog_cntr <= INV_S;
Expand All @@ -251,7 +251,7 @@ module ecc_pm_ctrl
end

CONV_E : begin // End of conversion from projective Mont (X,Y,Z) to affine normanl (x,y)
unique casez (ecc_cmd_reg)
unique case (ecc_cmd_reg)
SIGN_CMD : prog_cntr <= SIGN0_S;
default : prog_cntr <= NOP;
endcase
Expand All @@ -262,7 +262,7 @@ module ecc_pm_ctrl
end

INVq_E : begin // End of inversion mod q
unique casez (ecc_cmd_reg)
unique case (ecc_cmd_reg)
SIGN_CMD : prog_cntr <= SIGN1_S;
VER_PART0_CMD : prog_cntr <= VER0_P1_S;
default : prog_cntr <= NOP;
Expand Down Expand Up @@ -344,7 +344,7 @@ module ecc_pm_ctrl
/*
always_comb
begin : delay_flag
unique casez (prog_instr.opcode)
unique case (prog_instr.opcode)
UOP_DO_ADD_p : stall_flag = 1;
UOP_DO_SUB_p : stall_flag = 1;
UOP_DO_MUL_p : stall_flag = 1;
Expand Down
2 changes: 1 addition & 1 deletion src/ecc/rtl/ecc_pm_sequencer.sv
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Expand Up @@ -60,7 +60,7 @@ module ecc_pm_sequencer
end
else begin
if (ena) begin
unique casez(addra)
unique case(addra)
NOP : douta <= '0;
1 : douta <= '0;

Expand Down
4 changes: 2 additions & 2 deletions src/hmac/rtl/hmac_core.v
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Expand Up @@ -216,7 +216,7 @@ module hmac_core

first_round = (hmac_ctrl_reg == hmac_ctrl_last)? 1'b0 : 1'b1;

unique casez (hmac_ctrl_reg)
unique case (hmac_ctrl_reg)
CTRL_IPAD:
begin
if (first_round)
Expand Down Expand Up @@ -276,7 +276,7 @@ module hmac_core
hmac_ctrl_new = CTRL_IDLE;
hmac_ctrl_we = 0;

unique casez (hmac_ctrl_reg)
unique case (hmac_ctrl_reg)
CTRL_IDLE:
begin
ready_flag = 1;
Expand Down
14 changes: 7 additions & 7 deletions src/hmac_drbg/rtl/hmac_drbg.sv
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Expand Up @@ -196,7 +196,7 @@ module hmac_drbg
end
else
begin
unique casez (drbg_st_reg)
unique case (drbg_st_reg)
IDLE_ST: begin
if (init_cmd | next_cmd)
valid_reg <= 0;
Expand Down Expand Up @@ -229,7 +229,7 @@ module hmac_drbg
HMAC_init <= 0;
HMAC_next <= 0;
if (first_round) begin
unique casez(drbg_st_reg)
unique case(drbg_st_reg)
K10_ST: HMAC_init <= 1;
K11_ST: HMAC_next <= 1;
V1_ST: HMAC_init <= 1;
Expand Down Expand Up @@ -260,7 +260,7 @@ module hmac_drbg
end
else begin
if (first_round) begin
unique casez(drbg_st_reg)
unique case(drbg_st_reg)
INIT_ST: begin
K_reg <= K_init;
V_reg <= V_init;
Expand All @@ -283,7 +283,7 @@ module hmac_drbg
always_comb
begin : hmac_block_update
HMAC_key = K_reg;
unique casez(drbg_st_reg)
unique case(drbg_st_reg)
K10_ST: HMAC_block = {V_reg, cnt_reg, entropy, nonce[383:136]};
K11_ST: HMAC_block = {nonce[135:0], 1'h1, 875'b0, 12'h888};
V1_ST: HMAC_block = {V_reg, 1'h1, ZERO_PAD_V, V_SIZE};
Expand All @@ -304,7 +304,7 @@ module hmac_drbg
else if (zeroize)
cnt_reg <= '0;
else begin
unique casez (drbg_st_reg)
unique case (drbg_st_reg)
INIT_ST: cnt_reg <= '0;
NEXT_ST: cnt_reg <= cnt_reg + 1;
K2_INIT_ST: cnt_reg <= cnt_reg + 1;
Expand Down Expand Up @@ -342,11 +342,11 @@ module hmac_drbg

always_comb
begin: state_logic
unique casez (drbg_st_reg)
unique case (drbg_st_reg)
IDLE_ST: // IDLE WAIT
begin
if (HMAC_ready) begin
unique casez ({init_cmd, next_cmd})
unique case ({init_cmd, next_cmd})
2'b10 : drbg_next_st = INIT_ST;
2'b01 : drbg_next_st = NEXT_ST;
default: drbg_next_st = IDLE_ST;
Expand Down
2 changes: 1 addition & 1 deletion src/keyvault/rtl/kv.sv
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Expand Up @@ -171,7 +171,7 @@ always_comb begin : keyvault_ctrl
kv_reg_hwif_in.KEY_CTRL[entry].last_dword.hwclr = key_entry_clear[entry];

kv_reg_hwif_in.KEY_CTRL[entry].dest_valid.we = key_entry_ctrl_we[entry] & ~key_entry_clear[entry];
kv_reg_hwif_in.KEY_CTRL[entry].dest_valid.next = key_entry_dest_valid_next[entry];
kv_reg_hwif_in.KEY_CTRL[entry].dest_valid.next = {3'd0,key_entry_dest_valid_next[entry]};
kv_reg_hwif_in.KEY_CTRL[entry].last_dword.we = key_entry_ctrl_we[entry] & ~key_entry_clear[entry];
kv_reg_hwif_in.KEY_CTRL[entry].last_dword.next = key_entry_last_dword_next[entry];
end
Expand Down
4 changes: 2 additions & 2 deletions src/keyvault/rtl/kv_fsm.sv
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Expand Up @@ -86,7 +86,7 @@ always_comb ready = (kv_fsm_ps == KV_IDLE);
// Padding starts with a leading 1 after the valid data followed by 0's until
// the length of the valid data is stored in the last 4 dwords.
// HMAC adds 1024 bits to the length to account for the key
always_comb length_for_pad = (HMAC == 1) ? (num_dwords_data << 5) + 'd1024 : (num_dwords_data << 5);
always_comb length_for_pad = (HMAC == 1) ? (32'b0 | ((num_dwords_data << 5) + 'd1024)) : (32'b0 | (num_dwords_data << 5));

always_comb arc_KV_IDLE_KV_RW = start;
always_comb arc_KV_RW_KV_DONE = ((PAD == 0) | pcr_hash_extend) & (offset_nxt == num_dwords_total); //jump to done when we've written all dwords
Expand All @@ -107,7 +107,7 @@ always_comb begin : kv_fsm_comb
offset_nxt = '0;
pad_data = '0;
done = '0;
unique casez (kv_fsm_ps)
unique case (kv_fsm_ps)
KV_IDLE: begin
if (arc_KV_IDLE_KV_RW) kv_fsm_ns = KV_RW;
end
Expand Down
3 changes: 1 addition & 2 deletions src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv
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Expand Up @@ -2104,7 +2104,6 @@ else
({1{(mhpme_vec[i][9:0] == MHPME_INST_COMMIT_32B )}} & {tlu_i0_commit_cmt & exu_pmu_i0_pc4 & ~illegal_r}) |
({1{(mhpme_vec[i][9:0] == MHPME_INST_ALIGNED )}} & ifu_pmu_instr_aligned) |
({1{(mhpme_vec[i][9:0] == MHPME_INST_DECODED )}} & dec_pmu_instr_decoded) |
({1{(mhpme_vec[i][9:0] == MHPME_DECODE_STALL )}} & {dec_pmu_decode_stall}) |
({1{(mhpme_vec[i][9:0] == MHPME_INST_MUL )}} & {(pmu_i0_itype_qual == MUL)}) |
({1{(mhpme_vec[i][9:0] == MHPME_INST_DIV )}} & {dec_tlu_packet_r.pmu_divide & tlu_i0_commit_cmt & ~illegal_r}) |
({1{(mhpme_vec[i][9:0] == MHPME_INST_LOAD )}} & {(pmu_i0_itype_qual == LOAD)}) |
Expand Down Expand Up @@ -2716,7 +2715,7 @@ assign dec_tlu_presync_d = presync & dec_csr_any_unq_d & ~dec_csr_wen_unq_d;
assign dec_tlu_postsync_d = postsync & dec_csr_any_unq_d;

// allow individual configuration of these features
assign conditionally_illegal = ((csr_mitcnt0 | csr_mitcnt1 | csr_mitb0 | csr_mitb1 | csr_mitctl0 | csr_mitctl1) & !pt.TIMER_LEGAL_EN);
assign conditionally_illegal = ((csr_mitcnt0 | csr_mitcnt1 | csr_mitb0 | csr_mitb1 | csr_mitctl0 | csr_mitctl1) & ~|pt.TIMER_LEGAL_EN);

assign valid_csr = ( legal & (~(csr_dcsr | csr_dpc | csr_dmst | csr_dicawics | csr_dicad0 | csr_dicad0h | csr_dicad1 | csr_dicago) | dbg_tlu_halted_f)
& ~fast_int_meicpct & ~conditionally_illegal);
Expand Down
2 changes: 2 additions & 0 deletions src/riscv_core/veer_el2/rtl/el2_mem.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -128,6 +128,8 @@ else begin
assign ic_tag_perr = '0 ;
assign ic_rd_data = '0 ;
assign ictag_debug_rd_data = '0 ;
assign ic_debug_rd_data = '0 ;
assign ic_eccerr = '0;
end // else: !if( pt.ICACHE_ENABLE )


Expand Down
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