Fix reset if-else syntax on ctx FF blocks

chipsalliance · Jul 25, 2024 · 38a014c · 38a014c
1 parent bce6f7e
commit 38a014c
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Showing 2 changed files with 6 additions and 7 deletions.
diff --git a/src/axi/rtl/axi_sub_rd.sv b/src/axi/rtl/axi_sub_rd.sv
@@ -144,7 +144,7 @@ module axi_sub_rd import axi_pkg::*; #(
             txn_ctx <= '{default:0, burst:AXI_BURST_FIXED};
             txn_cnt <= '0;
         end
-        if (s_axi_if.arvalid && s_axi_if.arready) begin
+        else if (s_axi_if.arvalid && s_axi_if.arready) begin
             txn_ctx.addr  <= s_axi_if.araddr;
             txn_ctx.burst <= axi_burst_e'(s_axi_if.arburst);
             txn_ctx.size  <= s_axi_if.arsize;

diff --git a/src/axi/rtl/axi_sub_wr.sv b/src/axi/rtl/axi_sub_wr.sv
@@ -168,12 +168,11 @@ module axi_sub_wr import axi_pkg::*; #(
 
     always_comb req_matches_ex = (req_ctx.addr & ex_ctx[req_ctx.id].addr_mask) == ex_ctx[req_ctx.id].addr;
 
-    // TODO reset?
-    always_ff@(posedge clk/* or negedge rst_n*/) begin
-//        if (!rst_n) begin
-//            txn_ctx <= '{default:0};
-//        end
-        if (req_valid && req_ready) begin
+    always_ff@(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            txn_ctx <= '{default:0};
+        end
+        else if (req_valid && req_ready) begin
             txn_ctx.addr  <= req_ctx.addr;
             txn_ctx.burst <= req_ctx.burst;
             txn_ctx.size  <= req_ctx.size;