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Swap APB for AXI, replace all 'user' references with 'AXI ID'
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@calebofearth
calebofearth committed Jul 25, 2024
1 parent d467e3a commit 9f1e954
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Showing 26 changed files with 594 additions and 604 deletions.
49 changes: 11 additions & 38 deletions src/integration/rtl/caliptra_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -44,18 +44,9 @@ module caliptra_top
output logic jtag_tdo, // JTAG TDO
output logic jtag_tdoEn, // JTAG TDO enable

//APB Interface
input logic [`CALIPTRA_APB_ADDR_WIDTH-1:0] PADDR,
input logic [2:0] PPROT,
input logic PSEL,
input logic PENABLE,
input logic PWRITE,
input logic [`CALIPTRA_APB_DATA_WIDTH-1:0] PWDATA,
input logic [`CALIPTRA_APB_USER_WIDTH-1:0] PAUSER,

output logic PREADY,
output logic PSLVERR,
output logic [`CALIPTRA_APB_DATA_WIDTH-1:0] PRDATA,
//SoC AXI Interface
axi_if.w_sub s_axi_w_if,
axi_if.r_sub s_axi_r_if,

//QSPI Interface
output logic qspi_clk_o,
Expand Down Expand Up @@ -1171,9 +1162,10 @@ uart #(
soc_ifc_top #(
.AHB_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)),
.AHB_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE),
.APB_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)),
.APB_DATA_WIDTH(`CALIPTRA_APB_DATA_WIDTH),
.APB_USER_WIDTH(`CALIPTRA_APB_USER_WIDTH)
.AXI_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)),
.AXI_DATA_WIDTH(`CALIPTRA_AXI_DATA_WIDTH),
.AXI_ID_WIDTH (`CALIPTRA_AXI_ID_WIDTH ),
.AXI_USER_WIDTH(`CALIPTRA_AXI_USER_WIDTH)
)
soc_ifc_top1
(
Expand Down Expand Up @@ -1203,16 +1195,10 @@ soc_ifc_top1
// RV ECC Status Interface
.rv_ecc_sts(rv_ecc_sts),

//APB Interface with SoC
.paddr_i(PADDR[`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)-1:0]),
.psel_i(PSEL),
.penable_i(PENABLE),
.pwrite_i(PWRITE),
.pwdata_i(PWDATA),
.pauser_i(PAUSER),
.pready_o(PREADY),
.prdata_o(PRDATA),
.pslverr_o(PSLVERR),
//SoC AXI Interface
.s_axi_w_if(s_axi_w_if),
.s_axi_r_if(s_axi_r_if),

//AHB Interface with uC
.haddr_i (responder_inst[`CALIPTRA_SLAVE_SEL_SOC_IFC].haddr[`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)-1:0]),
.hwdata_i (responder_inst[`CALIPTRA_SLAVE_SEL_SOC_IFC].hwdata),
Expand Down Expand Up @@ -1321,17 +1307,4 @@ endgenerate
`CALIPTRA_ASSERT_KNOWN(AHB_MASTER_HRDATA_X, initiator_inst.hready ? initiator_inst.hrdata : '0, clk, !cptra_noncore_rst_b)
`CALIPTRA_ASSERT_NEVER(AHB_MASTER_HTRANS_BUSY, initiator_inst.htrans == 2'b01, clk, !cptra_noncore_rst_b)

`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PADDR_X, PADDR, clk, !cptra_rst_b)
`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PWDATA_X, PWDATA, clk, !cptra_rst_b)
`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PWRITE_X, PWRITE, clk, !cptra_rst_b)
`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PREADY_X, PREADY, clk, !cptra_rst_b)
`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PENABLE_X, PENABLE, clk, !cptra_rst_b)
`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PSEL_X, PSEL, clk, !cptra_rst_b)
`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PPROT_X, PPROT, clk, !cptra_rst_b)
`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PAUSER_X, PAUSER, clk, !cptra_rst_b)
`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PSLVERR_X, PSLVERR, clk, !cptra_rst_b)
`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PRDATA_X, PREADY ? PRDATA : '0, clk, !cptra_rst_b)

`CALIPTRA_ASSERT_NEVER(APB_MASTER_PPROT_ACTIVE, PPROT !== 3'b000, clk, !cptra_rst_b)

endmodule
7 changes: 4 additions & 3 deletions src/integration/rtl/config_defines.svh
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Original file line number Diff line number Diff line change
Expand Up @@ -22,9 +22,10 @@
`define CALIPTRA_AHB_MASTERS_NUM 4'd1 // Number of masters AHB
`define CALIPTRA_AHB_HADDR_SIZE 32 // bit-width AHB address haddr
`define CALIPTRA_AHB_HDATA_SIZE 64 // bit-width AHB data
`define CALIPTRA_APB_ADDR_WIDTH 32 // bit-width APB address
`define CALIPTRA_APB_DATA_WIDTH 32 // bit-width APB data
`define CALIPTRA_APB_USER_WIDTH 32 // bit-width APB PAUSER field
`define CALIPTRA_AXI_ADDR_WIDTH 32 // bit-width AXI address
`define CALIPTRA_AXI_DATA_WIDTH 32 // bit-width AXI data
`define CALIPTRA_AXI_USER_WIDTH 32 // bit-width AXI USER field
`define CALIPTRA_AXI_ID_WIDTH 5 // bit-width AXI ID field
`define CALIPTRA_QSPI_CS_WIDTH 2
`define CALIPTRA_QSPI_IO_WIDTH 4
`define CALIPTRA_SOC_SEC_STATE_WIDTH 3
Expand Down
26 changes: 13 additions & 13 deletions src/soc_ifc/rtl/mbox.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,7 @@ module mbox
output logic soc_mbox_data_avail,
output logic soc_req_mbox_lock,
output mbox_protocol_error_t mbox_protocol_error,
output logic mbox_inv_pauser_axs,
output logic mbox_inv_axi_id_axs,

//DMI reg access
input logic dmi_inc_rdptr,
Expand Down Expand Up @@ -146,10 +146,10 @@ assign mbox_error = read_error | write_error;

//Determine if this is a valid request from the requester side
//1) uC requests are valid if uc has lock
//2) SoC requests are valid if soc has lock and it's the user that locked it
//2) SoC requests are valid if soc has lock and it's the AXI ID that locked it
always_comb valid_requester = hwif_out.mbox_lock.lock.value &
((~req_data.soc_req & (~soc_has_lock || (mbox_fsm_ps == MBOX_EXECUTE_UC))) |
( req_data.soc_req & soc_has_lock & (req_data.user == hwif_out.mbox_user.user.value)));
( req_data.soc_req & soc_has_lock & (req_data.id == hwif_out.mbox_id.id.value)));

//Determine if this is a valid request from the receiver side
always_comb valid_receiver = hwif_out.mbox_lock.lock.value &
Expand All @@ -162,7 +162,7 @@ always_comb valid_receiver = hwif_out.mbox_lock.lock.value &
(~soc_has_lock & (mbox_fsm_ps == MBOX_EXECUTE_UC)))));

//We want to mask read data when
//Invalid user is trying to access the mailbox data
//Invalid ID is trying to access the mailbox data
always_comb mask_rdata = hwif_out.mbox_dataout.dataout.swacc & ~valid_receiver;

//move from idle to rdy for command when lock is acquired
Expand Down Expand Up @@ -191,7 +191,7 @@ always_comb arc_FORCE_MBOX_UNLOCK = hwif_out.mbox_unlock.unlock.value;
// Any register write or read by an INVALID agent results in the access
// being silently dropped.
// Assumption: uC (ROM, FMC, RT) will never make an invalid request.
// NOTE: Any APB agent can trigger the error at any point during a uC->SOC flow
// NOTE: Any AXI agent can trigger the error at any point during a uC->SOC flow
// by writing to mbox_status (since it's a valid_receiver).
// FIXED! valid_receiver is restricted by FSM state now.
always_comb arc_MBOX_RDY_FOR_CMD_MBOX_ERROR = (mbox_fsm_ps == MBOX_RDY_FOR_CMD) &&
Expand Down Expand Up @@ -340,7 +340,7 @@ always_comb begin : mbox_fsm_combo
end
end
//uC set execute, data is for the SoC
//If we're here, restrict reading to the user that requested the data
//If we're here, restrict reading to the AXI ID that requested the data
//Only SoC can read from mbox
//Only SoC can write to datain here to respond to uC
MBOX_EXECUTE_SOC: begin
Expand Down Expand Up @@ -379,10 +379,10 @@ always_comb begin : mbox_fsm_combo
endcase
end

// Any ol' PAUSER is fine for reg-reads (except dataout)
// NOTE: This only captures accesses by APB agents that are valid, but do not
// Any ol' AXI_ID is fine for reg-reads (except dataout)
// NOTE: This only captures accesses by AXI agents that are valid, but do not
// have lock. Invalid agent accesses are blocked by arbiter.
assign mbox_inv_pauser_axs = req_dv && req_data.soc_req && !req_hold &&
assign mbox_inv_axi_id_axs = req_dv && req_data.soc_req && !req_hold &&
!valid_requester && !valid_receiver &&
(req_data.write || hwif_out.mbox_dataout.dataout.swacc);

Expand Down Expand Up @@ -519,18 +519,18 @@ always_comb mbox_rd_full_nxt = rst_mbox_rdptr ? '0 : inc_rdptr & (mbox_rdptr ==
always_comb soc_req_mbox_lock = hwif_out.mbox_lock.lock.value & ~soc_has_lock & hwif_out.mbox_lock.lock.swmod & req_data.soc_req;

always_comb hwif_in.cptra_rst_b = rst_b;
always_comb hwif_in.mbox_user.user.next = req_data.user;
always_comb hwif_in.mbox_id.id.next = req_data.id;
always_comb hwif_in.mbox_status.mbox_fsm_ps.next = mbox_fsm_ps;

always_comb hwif_in.soc_req = req_data.soc_req;
//check the requesting user:
//check the requesting ID:
//don't update mailbox data if lock hasn't been acquired
//if uc has the lock, check that this request is from uc
//if soc has the lock, check that this request is from soc and user attributes match
//if soc has the lock, check that this request is from soc and ID attributes match
always_comb hwif_in.valid_requester = valid_requester;
always_comb hwif_in.valid_receiver = valid_receiver;

//indicate that requesting user is setting the lock
//indicate that requesting ID is setting the lock
always_comb hwif_in.lock_set = arc_MBOX_IDLE_MBOX_RDY_FOR_CMD;

//update dataout
Expand Down
12 changes: 6 additions & 6 deletions src/soc_ifc/rtl/mbox_csr.rdl
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Original file line number Diff line number Diff line change
Expand Up @@ -39,15 +39,15 @@ addrmap mbox_csr {
field {rset; sw=r; hw=r; hwclr=true; precedence=hw; swmod=true;} lock=0;
} mbox_lock;

// user register
// store user from interface when setting lock
// ID register
// store AXI ID from interface when setting lock
reg {
name="Mailbox User";
desc="Stores the user that locked the mailbox
name="Mailbox ID";
desc="Stores the AXI ID that locked the mailbox
[br]Caliptra Access: RO
[br]SOC Access: RO";
field {sw=r; hw=rw; we=lock_set;} user[32]=0;
} mbox_user;
field {sw=r; hw=rw; we=lock_set;} id[32]=0;
} mbox_id;

reg {
name="Mailbox Command";
Expand Down
32 changes: 16 additions & 16 deletions src/soc_ifc/rtl/mbox_csr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,7 @@ module mbox_csr (
//--------------------------------------------------------------------------
typedef struct packed{
logic mbox_lock;
logic mbox_user;
logic mbox_id;
logic mbox_cmd;
logic mbox_dlen;
logic mbox_datain;
Expand All @@ -84,7 +84,7 @@ module mbox_csr (

always_comb begin
decoded_reg_strb.mbox_lock = cpuif_req_masked & (cpuif_addr == 6'h0);
decoded_reg_strb.mbox_user = cpuif_req_masked & (cpuif_addr == 6'h4);
decoded_reg_strb.mbox_id = cpuif_req_masked & (cpuif_addr == 6'h4);
decoded_reg_strb.mbox_cmd = cpuif_req_masked & (cpuif_addr == 6'h8);
decoded_reg_strb.mbox_dlen = cpuif_req_masked & (cpuif_addr == 6'hc);
decoded_reg_strb.mbox_datain = cpuif_req_masked & (cpuif_addr == 6'h10);
Expand Down Expand Up @@ -114,8 +114,8 @@ module mbox_csr (
struct packed{
logic [31:0] next;
logic load_next;
} user;
} mbox_user;
} id;
} mbox_id;
struct packed{
struct packed{
logic [31:0] next;
Expand Down Expand Up @@ -190,8 +190,8 @@ module mbox_csr (
struct packed{
struct packed{
logic [31:0] value;
} user;
} mbox_user;
} id;
} mbox_id;
struct packed{
struct packed{
logic [31:0] value;
Expand Down Expand Up @@ -270,27 +270,27 @@ module mbox_csr (
end
assign hwif_out.mbox_lock.lock.value = field_storage.mbox_lock.lock.value;
assign hwif_out.mbox_lock.lock.swmod = decoded_reg_strb.mbox_lock && !decoded_req_is_wr;
// Field: mbox_csr.mbox_user.user
// Field: mbox_csr.mbox_id.id
always_comb begin
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.mbox_user.user.value;
next_c = field_storage.mbox_id.id.value;
load_next_c = '0;
if(hwif_in.lock_set) begin // HW Write - we
next_c = hwif_in.mbox_user.user.next;
next_c = hwif_in.mbox_id.id.next;
load_next_c = '1;
end
field_combo.mbox_user.user.next = next_c;
field_combo.mbox_user.user.load_next = load_next_c;
field_combo.mbox_id.id.next = next_c;
field_combo.mbox_id.id.load_next = load_next_c;
end
always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
if(~hwif_in.cptra_rst_b) begin
field_storage.mbox_user.user.value <= 32'h0;
end else if(field_combo.mbox_user.user.load_next) begin
field_storage.mbox_user.user.value <= field_combo.mbox_user.user.next;
field_storage.mbox_id.id.value <= 32'h0;
end else if(field_combo.mbox_id.id.load_next) begin
field_storage.mbox_id.id.value <= field_combo.mbox_id.id.next;
end
end
assign hwif_out.mbox_user.user.value = field_storage.mbox_user.user.value;
assign hwif_out.mbox_id.id.value = field_storage.mbox_id.id.value;
// Field: mbox_csr.mbox_cmd.command
always_comb begin
automatic logic [31:0] next_c;
Expand Down Expand Up @@ -585,7 +585,7 @@ module mbox_csr (
logic [9-1:0][31:0] readback_array;
assign readback_array[0][0:0] = (decoded_reg_strb.mbox_lock && !decoded_req_is_wr) ? field_storage.mbox_lock.lock.value : '0;
assign readback_array[0][31:1] = '0;
assign readback_array[1][31:0] = (decoded_reg_strb.mbox_user && !decoded_req_is_wr) ? field_storage.mbox_user.user.value : '0;
assign readback_array[1][31:0] = (decoded_reg_strb.mbox_id && !decoded_req_is_wr) ? field_storage.mbox_id.id.value : '0;
assign readback_array[2][31:0] = (decoded_reg_strb.mbox_cmd && !decoded_req_is_wr) ? field_storage.mbox_cmd.command.value : '0;
assign readback_array[3][31:0] = (decoded_reg_strb.mbox_dlen && !decoded_req_is_wr) ? field_storage.mbox_dlen.length.value : '0;
assign readback_array[4][31:0] = (decoded_reg_strb.mbox_datain && !decoded_req_is_wr) ? field_storage.mbox_datain.datain.value : '0;
Expand Down
14 changes: 8 additions & 6 deletions src/soc_ifc/rtl/mbox_csr_covergroups.svh
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Original file line number Diff line number Diff line change
Expand Up @@ -41,8 +41,8 @@

endgroup

/*----------------------- MBOX_CSR__MBOX_USER COVERGROUPS -----------------------*/
covergroup mbox_csr__mbox_user_bit_cg with function sample(input bit reg_bit);
/*----------------------- MBOX_CSR__MBOX_ID COVERGROUPS -----------------------*/
covergroup mbox_csr__mbox_id_bit_cg with function sample(input bit reg_bit);
option.per_instance = 1;
reg_bit_cp : coverpoint reg_bit {
bins value[2] = {0,1};
Expand All @@ -53,11 +53,11 @@
}

endgroup
covergroup mbox_csr__mbox_user_fld_cg with function sample(
input bit [32-1:0] user
covergroup mbox_csr__mbox_id_fld_cg with function sample(
input bit [32-1:0] id
);
option.per_instance = 1;
user_cp : coverpoint user {
id_cp : coverpoint id {
bins zero_val = {32'h0};
bins rand_val[64] = {[1:32'hFFFF_FFFE]};
bins ones_val = {{32{1'b1}}};
Expand Down Expand Up @@ -221,7 +221,8 @@
input bit [1-1:0] ecc_single_error,
input bit [1-1:0] ecc_double_error,
input bit [3-1:0] mbox_fsm_ps,
input bit [1-1:0] soc_has_lock
input bit [1-1:0] soc_has_lock,
input bit [15-1:0] mbox_rdptr
);
option.per_instance = 1;
status_cp : coverpoint status;
Expand Down Expand Up @@ -278,6 +279,7 @@
// illegal_bins TRANSITION_ERROR_EXECUTE_SOC = (mbox_fsm_state_e'(MBOX_ERROR) => mbox_fsm_state_e'(MBOX_EXECUTE_SOC));
}
soc_has_lock_cp : coverpoint soc_has_lock;
mbox_rdptr_cp : coverpoint mbox_rdptr;
status_edge_cp : coverpoint status {
bins rise = (0 => 1);
bins fall = (1 => 0);
Expand Down
16 changes: 8 additions & 8 deletions src/soc_ifc/rtl/mbox_csr_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,11 +16,11 @@ package mbox_csr_pkg;

typedef struct packed{
logic [31:0] next;
} mbox_csr__mbox_user__user__in_t;
} mbox_csr__mbox_id__id__in_t;

typedef struct packed{
mbox_csr__mbox_user__user__in_t user;
} mbox_csr__mbox_user__in_t;
mbox_csr__mbox_id__id__in_t id;
} mbox_csr__mbox_id__in_t;

typedef struct packed{
logic [31:0] next;
Expand Down Expand Up @@ -80,7 +80,7 @@ package mbox_csr_pkg;
logic valid_requester;
logic valid_receiver;
mbox_csr__mbox_lock__in_t mbox_lock;
mbox_csr__mbox_user__in_t mbox_user;
mbox_csr__mbox_id__in_t mbox_id;
mbox_csr__mbox_dataout__in_t mbox_dataout;
mbox_csr__mbox_execute__in_t mbox_execute;
mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__in_t mbox_status;
Expand All @@ -97,11 +97,11 @@ package mbox_csr_pkg;

typedef struct packed{
logic [31:0] value;
} mbox_csr__mbox_user__user__out_t;
} mbox_csr__mbox_id__id__out_t;

typedef struct packed{
mbox_csr__mbox_user__user__out_t user;
} mbox_csr__mbox_user__out_t;
mbox_csr__mbox_id__id__out_t id;
} mbox_csr__mbox_id__out_t;

typedef struct packed{
logic swmod;
Expand Down Expand Up @@ -190,7 +190,7 @@ package mbox_csr_pkg;

typedef struct packed{
mbox_csr__mbox_lock__out_t mbox_lock;
mbox_csr__mbox_user__out_t mbox_user;
mbox_csr__mbox_id__out_t mbox_id;
mbox_csr__mbox_cmd__out_t mbox_cmd;
mbox_csr__mbox_dlen__out_t mbox_dlen;
mbox_csr__mbox_datain__out_t mbox_datain;
Expand Down
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