Fix for truncated bits after casting logical shifts to the incorrect …

…width for lint fixes (#524) * fixing bugs caused during lint fixes where shifts were cast as the wrong width and bits are truncated fixed by removing the shifts and explicitly taking the bits required * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/lint_bug_fix' with updated timestamp and hash after successful run * updating smoke test to sha the entire mailbox at the start * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/lint_bug_fix' with updated timestamp and hash after successful run --------- Co-authored-by: Michael Norris <[email protected]>
chipsalliance · May 30, 2024 · b87af3b · b87af3b
1 parent f3a3306
commit b87af3b
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Showing 4 changed files with 88 additions and 57 deletions.
diff --git a/src/integration/test_suites/smoke_test_sha_accel/smoke_test_sha_accel.s b/src/integration/test_suites/smoke_test_sha_accel/smoke_test_sha_accel.s
@@ -56,6 +56,74 @@ _start:
    li x1, SHA512_ACC_CSR_LOCK_LOCK_MASK
    sw x1, 0(x3)
 
+    //SHA the entire mailbox
+    //Acquire SHA lock
+    li x3, CLP_SHA512_ACC_CSR_LOCK
+    lock_poll_loop4:
+        lw x5, 0(x3)
+        andi x5, x5, SHA512_ACC_CSR_LOCK_LOCK_MASK
+        bne x5, x0, lock_poll_loop4
+
+    //Set to Mailbox SHA384 Mode
+    li x3, CLP_SHA512_ACC_CSR_MODE
+    li x1, 0x00000006
+    sw x1, 0(x3)
+
+    // Load block from hw_data and write to Mailbox
+    li x3, CLP_SHA512_ACC_CSR_START_ADDRESS
+    li x4, CLP_SHA512_ACC_CSR_DLEN
+    // set t3 to constantly tracking current ptr
+    la t3, SHA384ExpRes
+    // x7 has the length in bytes
+    li x7, 0x20000
+    sw x7, 0(x4)
+
+    // Acquire lock before direct access to mailbox
+    li x3, CLP_MBOX_CSR_MBOX_LOCK
+    li x1, MBOX_CSR_MBOX_LOCK_LOCK_MASK
+    acquire_lock_loop2:
+        lw x5, 0(x3)
+        and x5, x5, x1
+        beq x5, x1, acquire_lock_loop2
+
+    // set execute
+    li x3, CLP_SHA512_ACC_CSR_EXECUTE
+    li x1, SHA512_ACC_CSR_EXECUTE_EXECUTE_MASK
+    sw x1, 0(x3)
+
+    // wait for SHA384 process
+    la x3, sha_intr_status
+    li x1, SHA512_ACC_CSR_STATUS_VALID_MASK
+    ready_loop4:
+        lw x5, 0(x3)
+        bne x5, x1, ready_loop4
+    sw x0, 0(x3) // clear status variable
+
+    // Read the data back from SHA Accelerator Digest register
+    li x3, CLP_SHA512_ACC_CSR_DIGEST_0
+    li x1, CLP_SHA512_ACC_CSR_DIGEST_11
+    read_result_loop4:
+        lw x5, 0(x3)
+        lw x7, 0(t3)
+        beq x5, x7, equal4
+        li x6, STDOUT
+        li x7, 0x01
+        sb x7, 0(x6)
+        equal4:
+            addi x3, x3, 4
+            addi t3, t3, 4
+            blt x3, x1, read_result_loop3
+
+    //Release SHA lock
+    li x3, CLP_SHA512_ACC_CSR_LOCK
+    li x1, SHA512_ACC_CSR_LOCK_LOCK_MASK
+    sw x1, 0(x3)
+
+    //Release MBOX lock
+    li x3, CLP_MBOX_CSR_MBOX_UNLOCK
+    li x1, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK
+    sw x1, 0(x3)
+
    //Acquire SHA lock
    li x3, CLP_SHA512_ACC_CSR_LOCK
    lock_poll_loop0:
@@ -345,9 +413,6 @@ _start:
         bne x5, x1, ready_loop3
     sw x0, 0(x3) // clear status variable
 
-//    //add this to start gets us to the result
-//    add t3, t3, x7
-
     // Read the data back from SHA Accelerator Digest register
     li x3, CLP_SHA512_ACC_CSR_DIGEST_0
     li x1, CLP_SHA512_ACC_CSR_DIGEST_11

diff --git a/src/integration/test_suites/smoke_test_sha_accel/smoke_test_sha_accel_vectors.s b/src/integration/test_suites/smoke_test_sha_accel/smoke_test_sha_accel_vectors.s
@@ -15,56 +15,20 @@
  */
 .section .dccm
 hw_data:
-// start of input message
-.word 0x61626380
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000018
+SHA384ExpRes:
 // expected value
-.word 0xDDAF35A1
-.word 0x93617ABA
-.word 0xCC417349
-.word 0xAE204131
-.word 0x12E6FA4E
-.word 0x89A97EA2
-.word 0x0A9EEEE6
-.word 0x4B55D39A
-.word 0x2192992A
-.word 0x274FC1A8
-.word 0x36BA3C23
-.word 0xA3FEEBBD
-.word 0x454D4423
-.word 0x643CE80E
-.word 0x2A9AC94F
-.word 0xA54CA49F
+.word 0xcad195e7
+.word 0xc3f2b250
+.word 0xb35ac78b
+.word 0x17b7c2f2
+.word 0x29e134b8
+.word 0x61f2d0be
+.word 0x15b7d954
+.word 0x6971f85e
+.word 0xc040693e
+.word 0x5a222188
+.word 0x7977fdea
+.word 0x6f89efee
 SHA512ShortMsg:
 // SHA512ShortMsgvector_2
 // vector length

diff --git a/src/soc_ifc/rtl/mbox.sv b/src/soc_ifc/rtl/mbox.sv
@@ -221,7 +221,7 @@ always_comb arc_MBOX_EXECUTE_SOC_MBOX_ERROR  = (mbox_fsm_ps == MBOX_EXECUTE_SOC)
 //Store the dlen as a ptr to the last entry
 always_comb latch_dlen_in_dws = arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_UC | arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_SOC | arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_SOC;
 always_comb mbox_dlen_in_dws = (hwif_out.mbox_dlen.length.value >= MBOX_SIZE_IN_BYTES) ? MBOX_SIZE_IN_DW[DEPTH_LOG2:0] :
-                               DEPTH_LOG2'(hwif_out.mbox_dlen.length.value >> 2) + (hwif_out.mbox_dlen.length.value[0] | hwif_out.mbox_dlen.length.value[1]);
+                               (hwif_out.mbox_dlen.length.value[DEPTH_LOG2+2:2]) + (hwif_out.mbox_dlen.length.value[0] | hwif_out.mbox_dlen.length.value[1]);
 //latched dlen is the smaller of the programmed dlen or the current wrptr
 //this avoids a case where a sender writes less than programmed and the receiver can read beyond that
 //if the mailbox is full (flag set when writing last entry), always take the programmed dlen

diff --git a/src/soc_ifc/rtl/sha512_acc_top.sv b/src/soc_ifc/rtl/sha512_acc_top.sv
@@ -71,7 +71,6 @@ module sha512_acc_top
   logic [MBOX_ADDR_W:0] mbox_rdptr;
   logic [MBOX_ADDR_W-1:0] mbox_start_addr, mbox_end_addr;
   logic mbox_read_to_end;
-  logic mbox_ptr_round_up;
   logic mbox_read_en;
   logic mbox_read_done;
   logic mbox_block_we;
@@ -303,10 +302,13 @@ always_comb core_digest_valid_q = core_digest_valid & ~(init_reg | next_reg);
 
   //byte address aligning to mailbox read pointer
   always_comb mbox_start_addr = hwif_out.START_ADDRESS.ADDR.value[MBOX_ADDR_W+1:2];
-  always_comb mbox_ptr_round_up = (|hwif_out.DLEN.LENGTH.value[1:0]);
+
+  //Convert DLEN to an end address. DLEN is in bytes, address is in dwords
   //detect overflow of end address to indicate we want to read to the end of the mailbox
-  always_comb {mbox_read_to_end, mbox_end_addr} = mbox_ptr_round_up ? mbox_start_addr + MBOX_ADDR_W'(hwif_out.DLEN.LENGTH.value>>2) + 1'b1 : 
-                                                                      mbox_start_addr + MBOX_ADDR_W'(hwif_out.DLEN.LENGTH.value>>2);
+  always_comb {mbox_read_to_end, mbox_end_addr} = mbox_start_addr + 
+                                                  hwif_out.DLEN.LENGTH.value[MBOX_ADDR_W+2:2] + 
+                                                  (hwif_out.DLEN.LENGTH.value[1] | hwif_out.DLEN.LENGTH.value[0]);
+
   always_comb mbox_read_done = (sha_fsm_ps == SHA_IDLE) | ~mailbox_mode | 
                                //If the DLEN overflowed our end address, just read to the end of the mailbox and stop
                                //Otherwise read until read pointer == end address