diff --git a/.github/workflows/doc-gen.yml b/.github/workflows/doc-gen.yml
new file mode 100644
index 000000000..3683d8f23
--- /dev/null
+++ b/.github/workflows/doc-gen.yml
@@ -0,0 +1,63 @@
+# docs: https://docs.github.com/en/actions/using-workflows/workflow-syntax-for-github-actions
+
+name: Register Documentation
+
+on:
+ workflow_dispatch:
+ pull_request:
+ push:
+ branches: ["main"]
+
+jobs:
+ build:
+ name: Build
+
+ runs-on: ubuntu-22.04
+
+ steps:
+ - uses: actions/checkout@v3
+
+ - name: Install peakrd-uvm
+ run: |
+ python3 -m pip install \
+ peakrdl-uvm==2.2.0 \
+ peakrdl-regblock==0.10.0 \
+ peakrdl-html==2.9.0 \
+ peakrdl-ipxact==3.3.0
+
+ - name: Generate docs
+ run: |
+ echo Running script
+ tools/scripts/reg_doc_gen.sh
+
+ - name: Stage documents
+ run: |
+ mkdir -p /tmp/pages-docs/0.8
+ cp -R src/integration/docs/caliptra_reg_html /tmp/pages-docs/0.8/internal-regs
+ cp -R src/soc_ifc/docs/caliptra_top_reg_html /tmp/pages-docs/0.8/external-regs
+ find /tmp/pages-docs
+
+ - name: Generate GitHub Pages artifacts
+ uses: actions/upload-pages-artifact@v1
+ with:
+ path: /tmp/pages-docs
+
+ deploy:
+ name: Deploy
+ needs: build
+ if: github.event_name == 'push'
+
+ permissions:
+ pages: write
+ id-token: write
+
+ environment:
+ name: github-pages
+ url: ${{ steps.deployment.outputs.page_url }}
+
+ runs-on: ubuntu-22.04
+
+ steps:
+ - name: Deploy to GitHub Pages
+ id: deployment
+ uses: actions/deploy-pages@v1
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 000000000..d0efbcf18
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,2 @@
+src/integration/docs/caliptra_reg_html/
+src/soc_ifc/docs/caliptra_top_reg_html/
diff --git a/src/integration/docs/caliptra_reg_html/.launcher_data/firefox/user.js b/src/integration/docs/caliptra_reg_html/.launcher_data/firefox/user.js
deleted file mode 100644
index 34b966f00..000000000
--- a/src/integration/docs/caliptra_reg_html/.launcher_data/firefox/user.js
+++ /dev/null
@@ -1,4 +0,0 @@
-user_pref("app.normandy.first_run", false);
-user_pref("toolkit.telemetry.reportingpolicy.firstRun", false);
-
-user_pref("security.fileuri.strict_origin_policy", false);
\ No newline at end of file
diff --git a/src/integration/docs/caliptra_reg_html/content/003e6f4d3661c51b1c10a9803fc659b4291f25e6.html b/src/integration/docs/caliptra_reg_html/content/003e6f4d3661c51b1c10a9803fc659b4291f25e6.html
deleted file mode 100644
index f6e0353bb..000000000
--- a/src/integration/docs/caliptra_reg_html/content/003e6f4d3661c51b1c10a9803fc659b4291f25e6.html
+++ /dev/null
@@ -1,83 +0,0 @@
-
-
-
-
Interrupt Status Aggregation Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0xc
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of any interrupt event
-of a given type. E.g. Notifications and Errors may drive
-to two separate interrupt registers. There may be
-multiple sources of Notifications or Errors that are
-aggregated into a single interrupt pin for that
-respective type. That pin feeds through this register
-in order to apply a global enablement of that interrupt
-event type.
-Nonsticky assertion.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
agg_sts
-
-
-
-
Interrupt Event Aggregation status bit
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x104
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
Interrupt Trigger Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x1c
- Size: 0x4
-
-
-
Description
-
-
Single bit for each interrupt event allows SW to manually
-trigger occurrence of that event. Upon SW write, the bit
-will pulse for 1 cycle then clear to 0.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error3_trig
-
-
-
-
Interrupt Trigger 3 bit
-
-
-
error2_trig
-
-
-
-
Interrupt Trigger 2 bit
-
-
-
error1_trig
-
-
-
-
Interrupt Trigger 1 bit
-
-
-
error0_trig
-
-
-
-
Interrupt Trigger 0 bit
-
-
-
Interrupt Trigger Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x20
- Size: 0x4
-
-
-
Description
-
-
Single bit for each interrupt event allows SW to manually
-trigger occurrence of that event. Upon SW write, the bit
-will pulse for 1 cycle then clear to 0.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_debug_locked_trig
-
-
-
-
Security State, Debug Locked transition trigger bit
-
-
-
notif_mbox_ecc_cor_trig
-
-
-
-
Mailbox ECC Single-bit Error (correctable) trigger bit
-
-
-
notif_cmd_avail_trig
-
-
-
-
Command Available trigger bit
-
-
-
SHA Accelerator Data Length
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
The length of data to be processed in bytes.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
LENGTH
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Security State
-
-
-
- Absolute Address:
- Base Offset: 0x44
- Size: 0x4
-
-
-
Description
-
-
Indicates current hardware security state.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
rsvd
-
-
-
-
Reserved field
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
scan_mode
-
-
-
-
scan mode signal observed at caliptra interface - only for debug mode as its used to flush assets -
-when truly in scan mode, everything will be BROKEN for functional reads!
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
debug_locked
-
-
-
-
Debug Locked
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
device_lifecycle
-
-
-
-
Device Lifecycle
-
-
- enum device_lifecycle_e
-
-
- DEVICE_UNPROVISIONED
- 0x0
- Unprovisioned
-
- DEVICE_MANUFACTURING
- 0x1
- Manufacturing
-
- DEVICE_PRODUCTION
- 0x3
- Production
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Key Vault Read Control Register
-
-
-
- Absolute Address:
- Base Offset: 0x610
- Size: 0x4
-
-
-
Description
-
-
Controls the Key Vault read access for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
rsvd
-
-
-
-
-
pcr_hash_extend
-
-
-
-
Requested entry is a PCR. This is used only for SHA to hash extend, it's NOP in all other engines
-
-
-
read_entry
-
-
-
-
Key Vault entry to retrieve the read data from for the engine
-
-
-
read_en
-
-
-
-
Indicates that the read data is to come from the key vault.
-Setting this bit to 1 initiates copying of data from the key vault.
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x10c
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
Flow Status
-
-
-
- Absolute Address:
- Base Offset: 0x3c
- Size: 0x4
-
-
-
Description
-
-
Reports the status of the firmware flows.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
mailbox_flow_done
-
-
-
-
Indicates Caliptra is has completed Mailbox Flow.
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
ready_for_fuses
-
-
-
-
Indicates Caliptra is ready for Fuses to be programmed.
-Read-only to both Caliptra and SOC.
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
ready_for_runtime
-
-
-
-
Indicates Caliptra is ready for Runtime Firmware Download
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
ready_for_fw
-
-
-
-
Indicates Caliptra is ready for Firmware Download
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Timer Config
-
-
-
- Absolute Address:
- Base Offset: 0xb0
- Size: 0x4
-
-
-
Description
-
-
Provides the clock period of the system clock.
-Used to standardize the RISC-V Standard MTIME count register.
-Clock Period is indicated as an integer number of picoseconds.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
clk_period
-
-
-
-
Period in (ps)
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
SHA256 component status register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
-
-
-
Description
-
-
One 2-bit register including the following flags:
-bit #0: READY : Indicates if the core is ready to take
- a control command and process the block.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
VALID
-
-
-
-
Status valid bit
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
READY
-
-
-
-
Status ready bit
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
SHA Accelerator User
-
-
-
- Absolute Address:
- Base Offset: 0x4
- Size: 0x4
-
-
-
Description
-
-
Stores the user that locked the SHA
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
USER
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Status Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x14
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of each interrupt event.
-Sticky, level assertion, write-1-to-clear.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error3_sts
-
-
-
-
Interrupt Event 3 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
error2_sts
-
-
-
-
Interrupt Event 2 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
error1_sts
-
-
-
-
Interrupt Event 1 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
error0_sts
-
-
-
-
Interrupt Event 0 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x218
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
Interrupt Status Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x14
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of each interrupt event.
-Sticky, level assertion, write-1-to-clear.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error3_sts
-
-
-
-
Interrupt Event 3 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
error2_sts
-
-
-
-
Interrupt Event 2 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
error1_sts
-
-
-
-
Interrupt Event 1 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
error0_sts
-
-
-
-
Interrupt Event 0 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
Interrupt Status Aggregation Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of any interrupt event
-of a given type. E.g. Notifications and Errors may drive
-to two separate interrupt registers. There may be
-multiple sources of Notifications or Errors that are
-aggregated into a single interrupt pin for that
-respective type. That pin feeds through this register
-in order to apply a global enablement of that interrupt
-event type.
-Nonsticky assertion.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
agg_sts
-
-
-
-
Interrupt Event Aggregation status bit
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x200
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x204
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
StickyDataVaultCtrl
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
- Array Dimensions: [10]
- Array Stride: +0x4
- Total Size: 0x28
-
-
-
Description
-
-
Controls for the Sticky Data Vault Entries
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
lock_entry
-
-
-
-
Lock writes to this entry. Writes will be suppressed when locked.
-
-
- Property
- Value
-
-
- resetsignal^.^.hard_reset_b
-
-
-
-
-
-
Interrupt Register Block
-
-
-
- Absolute Address:
- Base Offset: 0x800
- Size: 0x214
-
-
-
Description
-
-
Set of registers to implement interrupt functionality
-
-
-
Contents
-
-
-
-
HMAC384 component status register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
-
-
-
Description
-
-
One 2-bit register including the following flags:
-bit #0: READY : Indicates if the core is ready to take
- a control command and process the block.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
VALID
-
-
-
-
Status valid bit
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
READY
-
-
-
-
Status ready bit
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Valid User Register Lock
-
-
-
- Absolute Address:
- Base Offset: 0x5c
- Size: 0x4
- Array Dimensions: [5]
- Array Stride: +0x4
- Total Size: 0x14
-
-
-
Description
-
-
Valid PAUSER attributes for requests from SoC APB Interface.
-Each bit corresponds to locking the associated VALID_PAUSER register.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
LOCK
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
SHA256 component block register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x80
- Size: 0x4
- Array Dimensions: [16]
- Array Stride: +0x4
- Total Size: 0x40
-
-
-
Description
-
-
16 32-bit registers storing the 512-bit padded input.
-These registers are located at SHA256_base_address +
-0x0000_0080 to 0x0000_00BC in big-endian representation.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
BLOCK
-
-
-
-
Input message block field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
FW Update Reset
-
-
-
- Absolute Address:
- Base Offset: 0x624
- Size: 0x4
-
-
-
Description
-
-
Control register to assert FW update reset. When cleared to
-0, no reset is triggered. When set to 1, uc-only reset is asserted.
-Field automatically clears 1 cycle after being set.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
core_rst
-
-
-
-
FW Update reset to reset core
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x20c
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
SHA Accelerator Data Start Address
-
-
-
- Absolute Address:
- Base Offset: 0xc
- Size: 0x4
-
-
-
Description
-
-
The start address for FW controlled SHA performed on data stored in the mailbox.
-Start Address must be dword aligned.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ADDR
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
NMI Vector
-
-
-
- Absolute Address:
- Base Offset: 0x62c
- Size: 0x4
-
-
-
Description
-
-
32-bit register providing the jump vector for RISC-V to transition for NMI handling code.
-Default is the base address of ROM, but may be updated for enhanced handling by runtime images.
-Bit [0] is ignored to enforce half-word alignment of address.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
vec
-
-
-
-
NMI Vector
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x204
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
TRNG Status
-
-
-
- Absolute Address:
- Base Offset: 0xa8
- Size: 0x4
-
-
-
Description
-
-
TRNG Status register to indicate request and done
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
DATA_WR_DONE
-
-
-
-
Indicates that the requests TRNG Data is done and stored in the TRNG Data register.
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
DATA_REQ
-
-
-
-
Indicates that the requests TRNG Data is done and stored in the TRNG Data register.
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
STICKY_DATA_VAULT_ENTRY
-
-
-
- Absolute Address:
- Base Offset: 0x28
- Size: 0x4
- Array Dimensions: [10, 12]
- Array Stride: +0x4
- Total Size: 0x1e0
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
data
-
-
-
-
DataVault Entry
-
-
- Property
- Value
-
-
- resetsignal^.^.hard_reset_b
-
-
-
-
-
-
HMAC384 component control register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
One 3-bit register including the following flags:
-bit #0: INIT : Trigs the HMAC384 core to start the
- processing for the key and the first padded
- message block.
-bit #1: NEXT: Trigs the HMAC384 core to start the
- processing for the remining padded message block.
-bit #3: Zeroize all internal registers after HMAC process, to avoid SCA leakage.
-This register is located at HMAC384_base_address + 0x0000_0010
-After each software write, hardware will erase the register.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ZEROIZE
-
-
-
-
Zeroize all internal registers
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
NEXT
-
-
-
-
Control next command bit
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
INIT
-
-
-
-
Control init command bit
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x200
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
Key Vault Read Control Register
-
-
-
- Absolute Address:
- Base Offset: 0x608
- Size: 0x4
-
-
-
Description
-
-
Controls the Key Vault read access for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
rsvd
-
-
-
-
-
pcr_hash_extend
-
-
-
-
Requested entry is a PCR. This is used only for SHA to hash extend, it's NOP in all other engines
-
-
-
read_entry
-
-
-
-
Key Vault entry to retrieve the read data from for the engine
-
-
-
read_en
-
-
-
-
Indicates that the read data is to come from the key vault.
-Setting this bit to 1 initiates copying of data from the key vault.
-
-
-
Interrupt Register Block
-
-
-
- Absolute Address:
- Base Offset: 0x800
- Size: 0x208
-
-
-
Description
-
-
Set of registers to implement interrupt functionality
-for ECC
-
-
-
Contents
-
-
-
-
SHA256 component control register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
One 4-bit register including the following flags:
-bit #0: INIT : Trigs the SHA256 core to start the
- processing for the first padded message block.
-bit #1: NEXT: Trigs the SHA256 core to start the
- processing for the remining padded message block.
-bit #2: MODE : Indicates the SHA256 core to set dynamically
- the type of hashing algorithm. This can be:
- 0 for SHA256/224
- 1 for SHA256
-bit #3: Zeroize all internal registers after SHA process, to avoid SCA leakage.
-This register is located at SHA256_base_address + 0x0000_0010
-After each software write, hardware will erase the register.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ZEROIZE
-
-
-
-
Zeroize all internal registers
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
MODE
-
-
-
-
Control mode command bits
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
NEXT
-
-
-
-
Control next command bit
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
INIT
-
-
-
-
Control init command bit
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Boot Status
-
-
-
- Absolute Address:
- Base Offset: 0x38
- Size: 0x4
-
-
-
Description
-
-
Reports the boot status.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
status
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x204
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
Mailbox DataOut
-
-
-
- Absolute Address:
- Base Offset: 0x14
- Size: 0x4
-
-
-
Description
-
-
Data out register, read the next data from mailbox
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
dataout
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Status Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of each interrupt event.
-Sticky, level assertion, write-1-to-clear.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_sts
-
-
-
-
Command Done Interrupt status bit
-
-
-
Per-Event Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_en
-
-
-
-
Enable bit for Command Done
-
-
-
SHA Accelerator Execute
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
-
-
-
Description
-
-
For Streaming Function, indicates that the initiator is done streaming.
-For the Mailbox SHA Function, indicates that the SHA can begin execution.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
EXECUTE
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
TRNG Data
-
-
-
- Absolute Address:
- Base Offset: 0x78
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
Storage for the requested TRNG Data.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
DATA
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
HMAC384 component block register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x80
- Size: 0x4
- Array Dimensions: [32]
- Array Stride: +0x4
- Total Size: 0x80
-
-
-
Description
-
-
32 32-bit registers storing the 1024-bit padded input.
-These registers are located at HMAC384_base_address +
-0x0000_0080 to 0x0000_00FC in big-endian representation.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
BLOCK
-
-
-
-
Input message block field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x100
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
KEY_ENTRY
-
-
-
- Absolute Address:
- Base Offset: 0x600
- Size: 0x4
- Array Dimensions: [32, 12]
- Array Stride: +0x4
- Total Size: 0x600
-
-
-
Description
-
-
Key Entries are not readable or writeable by software
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
data
-
-
-
-
Key Entries are not accessible by software
-
-
- Property
- Value
-
-
- resetsignal^.^.hard_reset_b
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x184
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
-
fuse_runtime_svn
-
-
-
- Absolute Address:
- Base Offset: 0x2b8
- Size: 0x4
- Array Dimensions: [4]
- Array Stride: +0x4
- Total Size: 0x10
-
-
-
Description
-
-
Runtime SVN Fuse.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
svn
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x200
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
kv_reg
-
-
-
- Absolute Address:
- Base Offset: 0x10018000
- Size: 0xc04
-
-
-
Description
-
-
address map for keyvault
-
-
-
Contents
-
-
-
-
Interrupt Register Block
-
-
-
- Absolute Address:
- Base Offset: 0x800
- Size: 0x224
-
-
-
Description
-
-
Set of registers to implement interrupt functionality
-for soc interface.
-All registers have the following access privileges:
-
-
-
-
Contents
-
-
-
-
Interrupt Trigger Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x20
- Size: 0x4
-
-
-
Description
-
-
Single bit for each interrupt event allows SW to manually
-trigger occurrence of that event. Upon SW write, the bit
-will pulse for 1 cycle then clear to 0.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_trig
-
-
-
-
Interrupt Trigger 0 bit
-
-
-
PCR_ENTRY
-
-
-
- Absolute Address:
- Base Offset: 0x600
- Size: 0x4
- Array Dimensions: [32, 12]
- Array Stride: +0x4
- Total Size: 0x600
-
-
-
Description
-
-
Pcr Entries are read only
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
data
-
-
-
-
PCR Entries
-
-
- Property
- Value
-
-
- resetsignal^.^.hard_reset_b
-
-
-
-
-
-
Key Vault Read Control Register
-
-
-
- Absolute Address:
- Base Offset: 0x600
- Size: 0x4
-
-
-
Description
-
-
Controls the Key Vault read access for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
rsvd
-
-
-
-
-
pcr_hash_extend
-
-
-
-
Requested entry is a PCR. This is used only for SHA to hash extend, it's NOP in all other engines
-
-
-
read_entry
-
-
-
-
Key Vault entry to retrieve the read data from for the engine
-
-
-
read_en
-
-
-
-
Indicates that the read data is to come from the key vault.
-Setting this bit to 1 initiates copying of data from the key vault.
-
-
-
Interrupt Register Block
-
-
-
- Absolute Address:
- Base Offset: 0x800
- Size: 0x214
-
-
-
Description
-
-
Set of registers to implement interrupt functionality
-
-
-
Contents
-
-
-
-
Interrupt Register Block
-
-
-
- Absolute Address:
- Base Offset: 0x800
- Size: 0x214
-
-
-
Description
-
-
Set of registers to implement interrupt functionality
-
-
-
Contents
-
-
-
-
SHA512 component status register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
-
-
-
Description
-
-
One 2-bit register including the following flags:
-bit #0: READY : Indicates if the core is ready to take
- a control command and process the block.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
VALID
-
-
-
-
Status valid bit
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
READY
-
-
-
-
Status ready bit
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
clp
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x30030a24
-
-
-
Description
-
-
Address Map for Caliptra Register Space
-
-
-
Contents
-
-
-
- Offset
- Identifier
- Name
-
-
- 0x0FFFFFFF
- -
- -
-
-
- 0x10000000
- doe_reg -
-
-
-
-
-
- 0x10000A14
- -
- -
-
-
- 0x10008000
- ecc_reg -
-
-
-
-
-
- 0x10008A08
- -
- -
-
-
- 0x10010000
- hmac_reg -
-
-
-
-
-
- 0x10010A14
- -
- -
-
-
- 0x10018000
- kv_reg -
-
-
-
-
-
- 0x10018C04
- -
- -
-
-
- 0x1001A000
- pv_reg -
-
-
-
-
-
- 0x1001AC00
- -
- -
-
-
- 0x1001C000
- dv_reg -
-
-
-
-
-
- 0x1001C4C0
- -
- -
-
-
- 0x10020000
- sha512_reg -
-
-
-
-
-
- 0x10020A14
- -
- -
-
-
- 0x10028000
- sha256_reg -
-
-
-
-
-
- 0x10028A14
- -
- -
-
-
- 0x30020000
- mbox_csr -
-
-
-
-
-
- 0x30020024
- -
- -
-
-
- 0x30021000
- sha512_acc_csr -
-
-
-
-
-
- 0x30021A14
- -
- -
-
-
- 0x30030000
- soc_ifc_reg -
-
-
-
-
-
-
-
SHA Accelerator Digest
-
-
-
- Absolute Address:
- Base Offset: 0x20
- Size: 0x4
- Array Dimensions: [16]
- Array Stride: +0x4
- Total Size: 0x40
-
-
-
Description
-
-
16 32-bit registers storing the 512-bit digest output in
-big-endian representation.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
DIGEST
-
-
-
-
Output digest field
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x180
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
-
Interrupt Status Aggregation Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of any interrupt event
-of a given type. E.g. Notifications and Errors may drive
-to two separate interrupt registers. There may be
-multiple sources of Notifications or Errors that are
-aggregated into a single interrupt pin for that
-respective type. That pin feeds through this register
-in order to apply a global enablement of that interrupt
-event type.
-Nonsticky assertion.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
agg_sts
-
-
-
-
Interrupt Event Aggregation status bit
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x220
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
fuse_idevid_manuf_hsm_id
-
-
-
- Absolute Address:
- Base Offset: 0x32c
- Size: 0x4
- Array Dimensions: [4]
- Array Stride: +0x4
- Total Size: 0x10
-
-
-
Description
-
-
Manufacturer IDEVID Manufacturer’s HSM identifier (this is used to find the certificate chain from the boot media)
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
hsm_id
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
DOE component status register
-
-
-
- Absolute Address:
- Base Offset: 0x14
- Size: 0x4
-
-
-
Description
-
-
Provides status of the DOE block and the status of the flows it runs
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
DEOBF_SECRETS_CLEARED
-
-
-
-
Clear Secrets flow completed
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
FE_FLOW_DONE
-
-
-
-
FE flow completed
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
UDS_FLOW_DONE
-
-
-
-
UDS Flow Completed
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
VALID
-
-
-
-
Status valid bit - Indicates if the process is done and the results have been stored in the keyvault.
-
-
-
READY
-
-
-
-
Status ready bit - Indicates if the core is ready to take a control command and process the block.
-
-
-
Interrupt Trigger Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x20
- Size: 0x4
-
-
-
Description
-
-
Single bit for each interrupt event allows SW to manually
-trigger occurrence of that event. Upon SW write, the bit
-will pulse for 1 cycle then clear to 0.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_trig
-
-
-
-
Interrupt Trigger 0 bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
ECC component name register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
- Array Dimensions: [2]
- Array Stride: +0x4
- Total Size: 0x8
-
-
-
Description
-
-
Two 32-bit read-only registers repereseting of the name
-of ECC component. These registers are located at
-ECC_base_address + 0x0000_0000 and 0x0000_0004 addresses.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
NAME
-
-
-
-
-
ECC component SCA configuration register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x20
- Size: 0x4
-
-
-
Description
-
-
One 3-bit register to enable/disable the ECC SCA countermeasures.
-bit #0: POINT_RND_EN : Indicates if the base point randomization
- countermeasure is enabled.
-bit #1: MASK_SIGN_EN: Indicates if the mask countermeasure in SIGNING
- is enabled.
-bit #2: SCALAR_RND_EN: Indicates if the scalar ransomization countermeasure
- is enabled.
-
This register is located at ECC_base_address + 0x0000_0020.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
SCALAR_RND_EN
-
-
-
-
SCA scalar randomization field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
MASK_SIGN_EN
-
-
-
-
SCA mask signing field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
POINT_RND_EN
-
-
-
-
SCA point randomization field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Mailbox Status
-
-
-
- Absolute Address:
- Base Offset: 0x1c
- Size: 0x4
-
-
-
Description
-
-
Status of the mailbox command
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
soc_has_lock - SoC Acquired the Lock
-
-
-
-
Indicates that the current lock was acquired by the SoC
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
mbox_fsm_ps - Mailbox FSM Present State
-
-
-
-
Indicates the present state of the mailbox FSM
-
-
-
- enum mbox_fsm_e
-
-
- MBOX_IDLE
- 0x0
- Mailbox is idle
-
- MBOX_RDY_FOR_CMD
- 0x1
- Mailbox is waiting for command
-
- MBOX_RDY_FOR_DLEN
- 0x3
- Mailbox is waiting for data length
-
- MBOX_RDY_FOR_DATA
- 0x2
- Mailbox is ready for data
-
- MBOX_EXECUTE_UC
- 0x6
- Mailbox has data for uC
-
- MBOX_EXECUTE_SOC
- 0x4
- Mailbox has data for SoC
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
ecc_double_error - Mailbox ECC Double Error
-
-
-
-
Indicates an uncorrectable ECC double-bit error
-was detected while reading dataout.
-Firmware developers are advised to set the command
-status to CMD_FAILURE in response.
-Auto-clears when mbox_execute field is cleared.
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
ecc_single_error - Mailbox ECC Single Error
-
-
-
-
Indicates a correctable ECC single-bit error was
-detected and corrected while reading dataout.
-Auto-clears when mbox_execute field is cleared.
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
status - Mailbox Status
-
-
-
-
Indicates the status of mailbox command
-
-
-
- enum mbox_status_e
-
-
- CMD_BUSY
- 0x0
- Receiver is busy, command is not yet complete.
-
- DATA_READY
- 0x1
- Requested data is ready in the mailbox.
-
- CMD_COMPLETE
- 0x2
- Requested command is complete.
-
- CMD_FAILURE
- 0x3
- The requested command experienced a failure.
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x104
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Trigger Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x20
- Size: 0x4
-
-
-
Description
-
-
Single bit for each interrupt event allows SW to manually
-trigger occurrence of that event. Upon SW write, the bit
-will pulse for 1 cycle then clear to 0.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_trig
-
-
-
-
Interrupt Trigger 0 bit
-
-
-
Interrupt Status Aggregation Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of any interrupt event
-of a given type. E.g. Notifications and Errors may drive
-to two separate interrupt registers. There may be
-multiple sources of Notifications or Errors that are
-aggregated into a single interrupt pin for that
-respective type. That pin feeds through this register
-in order to apply a global enablement of that interrupt
-event type.
-Nonsticky assertion.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
agg_sts
-
-
-
-
Interrupt Event Aggregation status bit
-
-
-
Per-Event Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_debug_locked_en
-
-
-
-
Enable bit for Security State, Debug Locked transition
-
-
-
notif_mbox_ecc_cor_en
-
-
-
-
Enable bit for Mailbox ECC Single-bit Error (correctable)
-
-
-
notif_cmd_avail_en
-
-
-
-
Enable bit for Command Available
-
-
-
ECC component verify R result register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x400
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
12 32-bit registers storing the result of verifying operation.
-Firmware is responsible for comparing the computed result with
-the signature R, and if they are equal the signature is valid.
-The verify R result should be in [1 : q-1] while q is the group
-order of the Secp384r1 curve.
-These registers are located at ECC_base_address +
-0x0000_0400 to 0x0000_042C in big-endian representation.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
VERIFY_R
-
-
-
-
Output digest field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Interrupt Status Aggregation Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0xc
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of any interrupt event
-of a given type. E.g. Notifications and Errors may drive
-to two separate interrupt registers. There may be
-multiple sources of Notifications or Errors that are
-aggregated into a single interrupt pin for that
-respective type. That pin feeds through this register
-in order to apply a global enablement of that interrupt
-event type.
-Nonsticky assertion.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
agg_sts
-
-
-
-
Interrupt Event Aggregation status bit
-
-
-
Key Vault Write Control Register
-
-
-
- Absolute Address:
- Base Offset: 0x610
- Size: 0x4
-
-
-
Description
-
-
Controls the Key Vault write access for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
rsvd
-
-
-
-
-
ecc_msg_dest_valid
-
-
-
-
ECC MSG is a valid destination
-
-
-
ecc_seed_dest_valid
-
-
-
-
ECC SEED is a valid destination
-
-
-
ecc_pkey_dest_valid
-
-
-
-
ECC PKEY is a valid destination
-
-
-
sha_block_dest_valid
-
-
-
-
SHA BLOCK is a valid destination
-
-
-
hmac_block_dest_valid
-
-
-
-
HMAC BLOCK is a valid destination
-
-
-
hmac_key_dest_valid
-
-
-
-
HMAC KEY is a valid destination
-
-
-
write_entry
-
-
-
-
Key Vault entry to store the result
-
-
-
write_en
-
-
-
-
Indicates that the result is to be stored in the key vault.
-Setting this bit to 1 will copy the result to the keyvault when it is ready.
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x100
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
Fuse Write Done
-
-
-
- Absolute Address:
- Base Offset: 0xac
- Size: 0x4
-
-
-
Description
-
-
Writes to fuse registers are completed. After the done bit is set, any subsequent writes to a fuse register will be dropped unless there is a power cycle or a warm reset or caliptra FW allows a write (negotiated through a mailbox command).
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
done
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Mailbox Command
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
-
-
-
Description
-
-
Command requested for data in mailbox
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
command
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x210
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
Interrupt Trigger Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x1c
- Size: 0x4
-
-
-
Description
-
-
Single bit for each interrupt event allows SW to manually
-trigger occurrence of that event. Upon SW write, the bit
-will pulse for 1 cycle then clear to 0.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error3_trig
-
-
-
-
Interrupt Trigger 3 bit
-
-
-
error2_trig
-
-
-
-
Interrupt Trigger 2 bit
-
-
-
error1_trig
-
-
-
-
Interrupt Trigger 1 bit
-
-
-
error0_trig
-
-
-
-
Interrupt Trigger 0 bit
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x180
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
HMAC384 component tag register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x100
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
12 32-bit registers storing the 384-bit digest output.
-These registers are located at HMAC384_base_address +
-0x0000_0100 to 0x0000_012C in big-endian representation.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
TAG
-
-
-
-
Output tag field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
fuse_idevid_cert_attr
-
-
-
- Absolute Address:
- Base Offset: 0x2cc
- Size: 0x4
- Array Dimensions: [24]
- Array Stride: +0x4
- Total Size: 0x60
-
-
-
Description
-
-
Manufacturer IEEE IDevID Certificate Gen Attributes.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cert
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
dv_reg
-
-
-
- Absolute Address:
- Base Offset: 0x1001c000
- Size: 0x4c0
-
-
-
Description
-
-
address map for keyvault
-
-
-
Contents
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x200
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x104
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
Firmware Error Encoding
-
-
-
- Absolute Address:
- Base Offset: 0x14
- Size: 0x4
-
-
-
Description
-
-
Encoded error value for firmware errors.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_code
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x108
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x210
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
Key Vault Status Register
-
-
-
- Absolute Address:
- Base Offset: 0x604
- Size: 0x4
-
-
-
Description
-
-
Reports the Key Vault flow status for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ERROR - Key Vault Error
-
-
-
-
Indicates the error status of a key vault flow
-
-
- enum kv_error_e
-
-
- SUCCESS
- 0x0
- Key Vault flow was successful
-
- KV_READ_FAIL
- 0x1
- Key Vault Read flow failed
-
- KV_WRITE_FAIL
- 0x2
- Key Vault Write flow failed
-
-
-
-
VALID
-
-
-
-
Key Vault flow is done
-
-
-
READY
-
-
-
-
Key Vault control is ready for use
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x208
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
fuse_key_manifest_pk_hash_mask
-
-
-
- Absolute Address:
- Base Offset: 0x280
- Size: 0x4
-
-
-
Description
-
-
Key Manifest Mask Fuse.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
mask
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x188
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x100
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
Generate PCR Hash
-
-
-
- Absolute Address:
- Base Offset: 0x610
- Size: 0x4
-
-
-
Description
-
-
Enables the HW controlled function to generate a hash of all PCR registers.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
FLOW_EN
-
-
-
-
Setting this register starts the flow.
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Interrupt Trigger Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x20
- Size: 0x4
-
-
-
Description
-
-
Single bit for each interrupt event allows SW to manually
-trigger occurrence of that event. Upon SW write, the bit
-will pulse for 1 cycle then clear to 0.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_trig
-
-
-
-
Interrupt Trigger 0 bit
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x210
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
Key Vault Status Register
-
-
-
- Absolute Address:
- Base Offset: 0x614
- Size: 0x4
-
-
-
Description
-
-
Reports the Key Vault flow status for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ERROR - Key Vault Error
-
-
-
-
Indicates the error status of a key vault flow
-
-
- enum kv_error_e
-
-
- SUCCESS
- 0x0
- Key Vault flow was successful
-
- KV_READ_FAIL
- 0x1
- Key Vault Read flow failed
-
- KV_WRITE_FAIL
- 0x2
- Key Vault Write flow failed
-
-
-
-
VALID
-
-
-
-
Key Vault flow is done
-
-
-
READY
-
-
-
-
Key Vault control is ready for use
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x108
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Status Aggregation Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0xc
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of any interrupt event
-of a given type. E.g. Notifications and Errors may drive
-to two separate interrupt registers. There may be
-multiple sources of Notifications or Errors that are
-aggregated into a single interrupt pin for that
-respective type. That pin feeds through this register
-in order to apply a global enablement of that interrupt
-event type.
-Nonsticky assertion.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
agg_sts
-
-
-
-
Interrupt Event Aggregation status bit
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x208
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
Hardware Error Non-Fatal
-
-
-
- Absolute Address:
- Base Offset: 0x4
- Size: 0x4
-
-
-
Description
-
-
Indicates non-fatal hardware error.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_code
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Key Vault Read Control Register
-
-
-
- Absolute Address:
- Base Offset: 0x608
- Size: 0x4
-
-
-
Description
-
-
Controls the Key Vault read access for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
rsvd
-
-
-
-
-
pcr_hash_extend
-
-
-
-
Requested entry is a PCR. This is used only for SHA to hash extend, it's NOP in all other engines
-
-
-
read_entry
-
-
-
-
Key Vault entry to retrieve the read data from for the engine
-
-
-
read_en
-
-
-
-
Indicates that the read data is to come from the key vault.
-Setting this bit to 1 initiates copying of data from the key vault.
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x210
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
SHA256 component name register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
- Array Dimensions: [2]
- Array Stride: +0x4
- Total Size: 0x8
-
-
-
Description
-
-
Two 32-bit read-only registers repereseting of the name
-of SHA256 component. These registers are located at
-SHA256_base_address + 0x0000_0000 and 0x0000_0004 addresses.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
NAME
-
-
-
-
-
Interrupt Status Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x14
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of each interrupt event.
-Sticky, level assertion, write-1-to-clear.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error3_sts
-
-
-
-
Interrupt Event 3 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
error2_sts
-
-
-
-
Interrupt Event 2 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
error1_sts
-
-
-
-
Interrupt Event 1 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
error0_sts
-
-
-
-
Interrupt Event 0 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x210
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
HMAC384 component name register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
- Array Dimensions: [2]
- Array Stride: +0x4
- Total Size: 0x8
-
-
-
Description
-
-
Two 32-bit read-only registers repereseting of the name
-of HMAC384 component. These registers are located at
-HMAC384_base_address + 0x0000_0000 and 0x0000_0004 addresses.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
NAME
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x208
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
KEY_CTRL
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
- Array Dimensions: [32]
- Array Stride: +0x4
- Total Size: 0x80
-
-
-
Description
-
-
Controls for each keyvault and pcr entry
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
last_dword
-
-
-
-
Stores the offset of the last valid dword, used to indicate last cycle on reads.
-
-
- Property
- Value
-
-
- resetsignal^.^.hard_reset_b
-
-
-
-
-
-
dest_valid
-
-
-
-
Destination valid bits stored as an array for ease of use in RTL.
-
-
-
- Property
- Value
-
-
- resetsignal^.^.hard_reset_b
-
-
-
-
-
-
rsvd1
-
-
-
-
-
rsvd0
-
-
-
-
-
clear
-
-
-
-
Clear the data stored in this entry. Lock write will prevent this clear.
-
-
-
lock_use
-
-
-
-
Lock use of this entry. Reads will be suppressed and an error will be recorded.
-
-
- Property
- Value
-
-
- resetsignal^.^.core_only_rst_b
-
-
-
-
-
-
lock_wr
-
-
-
-
Lock writes to this entry. Writes will be suppressed and an error will be recorded.
-
-
- Property
- Value
-
-
- resetsignal^.^.core_only_rst_b
-
-
-
-
-
-
Interrupt Status Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of each interrupt event.
-Sticky, level assertion, write-1-to-clear.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_debug_locked_sts
-
-
-
-
Security State, Debug Locked transition status bit
-
-
-
notif_mbox_ecc_cor_sts
-
-
-
-
Mailbox ECC Single-bit Error (correctable) status bit
-
-
-
notif_cmd_avail_sts
-
-
-
-
Command Available status bit
-
-
-
NonStickyLockableScratchReg
-
-
-
- Absolute Address:
- Base Offset: 0x438
- Size: 0x4
- Array Dimensions: [10]
- Array Stride: +0x4
- Total Size: 0x28
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
data
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Per-Event Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x4
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error3_en
-
-
-
-
Enable bit for Event 3
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
error2_en
-
-
-
-
Enable bit for Event 2
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
error1_en
-
-
-
-
Enable bit for Event 1
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
error0_en
-
-
-
-
Enable bit for Event 0
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
ECC component IV register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x480
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
12 32-bit registers storing the 384-bit IV required
-for SCA countermeasures to randomize the inputs with no change
-on the ECC outputs.
-The IV can be any 384-bit value in [0 : 2^384-1].
-These registers are located at ECC_base_address +
-0x0000_0480 to 0x0000_04AC in big-endian representation.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
IV
-
-
-
-
Input IV field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Per-Event Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x4
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error3_en
-
-
-
-
Enable bit for Event 3
-
-
-
error2_en
-
-
-
-
Enable bit for Event 2
-
-
-
error1_en
-
-
-
-
Enable bit for Event 1
-
-
-
error0_en
-
-
-
-
Enable bit for Event 0
-
-
-
Per-Type Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event type that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_en
-
-
-
-
Global enable bit for all events of type 'Notification'
-
-
-
error_en
-
-
-
-
Global enable bit for all events of type 'Error'
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x20c
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Status Aggregation Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0xc
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of any interrupt event
-of a given type. E.g. Notifications and Errors may drive
-to two separate interrupt registers. There may be
-multiple sources of Notifications or Errors that are
-aggregated into a single interrupt pin for that
-respective type. That pin feeds through this register
-in order to apply a global enablement of that interrupt
-event type.
-Nonsticky assertion.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
agg_sts
-
-
-
-
Interrupt Event Aggregation status bit
-
-
-
Interrupt Status Aggregation Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of any interrupt event
-of a given type. E.g. Notifications and Errors may drive
-to two separate interrupt registers. There may be
-multiple sources of Notifications or Errors that are
-aggregated into a single interrupt pin for that
-respective type. That pin feeds through this register
-in order to apply a global enablement of that interrupt
-event type.
-Nonsticky assertion.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
agg_sts
-
-
-
-
Interrupt Event Aggregation status bit
-
-
-
SHA Accelerator Mode
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
-
-
-
Description
-
-
Stores the requested mode for the SHA to execute.
-SHA Supports both SHA384 and SHA512 modes of operation.
-SHA Supports streaming mode - SHA is computed on a stream of incoming data to datain register.
- mailbox mode - SHA is computed on LENGTH bytes of data stored in the mailbox from START_ADDRESS.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ENDIAN_TOGGLE - Endianness Toggle for SHA in mailbox mode
-
-
-
-
Default behavior assumes that data in mailbox is little endian,
-When set to 0, data from mailbox will be swizzled from little to big endian at the byte level.
-When set to 1, data from the mailbox will be loaded into SHA as-is.
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
MODE
-
-
-
-
-
- enum sha_cmd_e
-
-
- SHA_STREAM_384
- 0x0
- SHA is in SHA384, streaming mode
-
- SHA_STREAM_512
- 0x1
- SHA is in SHA512, streaming mode
-
- SHA_MBOX_384
- 0x2
- SHA is in SHA384, mailbox mode
-
- SHA_MBOX_512
- 0x3
- SHA is in SHA512, mailbox mode
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x210
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
Interrupt Trigger Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x20
- Size: 0x4
-
-
-
Description
-
-
Single bit for each interrupt event allows SW to manually
-trigger occurrence of that event. Upon SW write, the bit
-will pulse for 1 cycle then clear to 0.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_trig
-
-
-
-
Interrupt Trigger 0 bit
-
-
-
Firmware Error Fatal
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
-
-
-
Description
-
-
Indicates fatal firmware error.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_code
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Valid User Registers
-
-
-
- Absolute Address:
- Base Offset: 0x48
- Size: 0x4
- Array Dimensions: [5]
- Array Stride: +0x4
- Total Size: 0x14
-
-
-
Description
-
-
Valid PAUSER attributes for requests from SoC APB Interface.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
PAUSER
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
fuse_life_cycle
-
-
-
- Absolute Address:
- Base Offset: 0x33c
- Size: 0x4
-
-
-
Description
-
-
Caliptra Boot Media Integrated mode usage only. SOCs that build with a Boot Media Independent profile don’t have to account for these fuses.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
life_cycle
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Per-Event Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_en
-
-
-
-
Enable bit for Command Done Interrupt
-
-
-
Per-Type Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event type that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_en
-
-
-
-
Global enable bit for all events of type 'Notification'
-
-
-
error_en
-
-
-
-
Global enable bit for all events of type 'Error'
-
-
-
Interrupt Status Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x14
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of each interrupt event.
-Sticky, level assertion, write-1-to-clear.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error3_sts
-
-
-
-
Interrupt Event 3 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
error2_sts
-
-
-
-
Interrupt Event 2 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
error1_sts
-
-
-
-
Interrupt Event 1 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
error0_sts
-
-
-
-
Interrupt Event 0 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
Per-Event Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x4
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_internal_en
-
-
-
-
Enable bit for Internal Errors
-
-
-
DOE Command control register
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
Controls the de-obfuscation command to run
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
DEST
-
-
-
-
Key Vault entry to store the result.
-
-
-
CMD
-
-
-
-
Indicates the command for DOE to run
-
-
- enum doe_cmd_e
-
-
- DOE_IDLE
- 0x0
- DOE is in idle state.
-
- DOE_UDS
- 0x1
- Request DOE to run UDS flow.
-
- DOE_FE
- 0x2
- Request DOE to run FE flow.
-
- DOE_CLEAR_OBF_SECRETS
- 0x3
- Sets the UDS, FE, and OBF KEY flops to zeroes.
-
-
-
-
Interrupt Trigger Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x1c
- Size: 0x4
-
-
-
Description
-
-
Single bit for each interrupt event allows SW to manually
-trigger occurrence of that event. Upon SW write, the bit
-will pulse for 1 cycle then clear to 0.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error3_trig
-
-
-
-
Interrupt Trigger 3 bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
error2_trig
-
-
-
-
Interrupt Trigger 2 bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
error1_trig
-
-
-
-
Interrupt Trigger 1 bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
error0_trig
-
-
-
-
Interrupt Trigger 0 bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x204
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
DEBUG & MANUF SERVICE REG
-
-
-
- Absolute Address:
- Base Offset: 0xb8
- Size: 0x4
-
-
-
Description
-
-
JTAG in debug/manuf mode or SOC can write to this register for ROM/FW defined skips or services; ROM/FW maintains the defintion of these bits.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
DATA
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
FW Update Reset Wait Cycles
-
-
-
- Absolute Address:
- Base Offset: 0x628
- Size: 0x4
-
-
-
Description
-
-
Control register to set the number of cycles for which FW update reset must be asserted. Default is 5. Max value is 255 (8 bit).
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
wait_cycles
-
-
-
-
FW Update reset wait cycles
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
ECC component seed register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x80
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
12 32-bit registers storing the 384-bit seed for keygen.
-The seed can be any 384-bit value in [0 : 2^384-1].
-These registers are located at ECC_base_address +
-0x0000_0080 to 0x0000_00AC in big-endian representation.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
SEED
-
-
-
-
Input seed field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Key Vault Status Register
-
-
-
- Absolute Address:
- Base Offset: 0x60c
- Size: 0x4
-
-
-
Description
-
-
Reports the Key Vault flow status for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ERROR - Key Vault Error
-
-
-
-
Indicates the error status of a key vault flow
-
-
- enum kv_error_e
-
-
- SUCCESS
- 0x0
- Key Vault flow was successful
-
- KV_READ_FAIL
- 0x1
- Key Vault Read flow failed
-
- KV_WRITE_FAIL
- 0x2
- Key Vault Write flow failed
-
-
-
-
VALID
-
-
-
-
Key Vault flow is done
-
-
-
READY
-
-
-
-
Key Vault control is ready for use
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x204
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
Generic Output Wires
-
-
-
- Absolute Address:
- Base Offset: 0xc8
- Size: 0x4
- Array Dimensions: [2]
- Array Stride: +0x4
- Total Size: 0x8
-
-
-
Description
-
-
Generic output wires connected to SoC interface.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
generic_wires
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Firmware Error Non-Fatal
-
-
-
- Absolute Address:
- Base Offset: 0xc
- Size: 0x4
-
-
-
Description
-
-
Indicates non-fatal firmware error.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_code
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
DOE component IV register
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
- Array Dimensions: [4]
- Array Stride: +0x4
- Total Size: 0x10
-
-
-
Description
-
-
4 32-bit registers storing the 128-bit IV.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
IV
-
-
-
-
IV input field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Unique Device Secret
-
-
-
- Absolute Address:
- Base Offset: 0x200
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
Obfuscated UDS.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
seed
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
ecc_reg
-
-
-
- Absolute Address:
- Base Offset: 0x10008000
- Size: 0xa08
-
-
-
Description
-
-
address maps for ecc register space
-
-
-
Contents
-
-
-
- Offset
- Identifier
- Name
-
-
- 0x000
- ECC_NAME[2] ECC component name register type definition
-
-
-
-
-
- 0x008
- ECC_VERSION[2] ECC component version register type definition
-
-
-
-
-
- 0x010
- ECC_CTRL ECC component control register type definition
-
-
-
-
-
- 0x014
- -
- -
-
-
- 0x018
- ECC_STATUS ECC component status register type definition
-
-
-
-
-
- 0x01C
- -
- -
-
-
- 0x020
- ECC_SCACONFIG ECC component SCA configuration register type definition
-
-
-
-
-
- 0x024
- -
- -
-
-
- 0x080
- ECC_SEED[12] ECC component seed register type definition
-
-
-
-
-
- 0x0B0
- -
- -
-
-
- 0x100
- ECC_MSG[12] ECC component hashed message register type definition
-
-
-
-
-
- 0x130
- -
- -
-
-
- 0x180
- ECC_PRIVKEY[12] ECC component private key register type definition
-
-
-
-
-
- 0x1B0
- -
- -
-
-
- 0x200
- ECC_PUBKEY_X[12] ECC component public key (x) register type definition
-
-
-
-
-
- 0x230
- -
- -
-
-
- 0x280
- ECC_PUBKEY_Y[12] ECC component public key (y) register type definition
-
-
-
-
-
- 0x2B0
- -
- -
-
-
- 0x300
- ECC_SIGN_R[12] ECC component signature R register type definition
-
-
-
-
-
- 0x330
- -
- -
-
-
- 0x380
- ECC_SIGN_S[12] ECC component signature S register type definition
-
-
-
-
-
- 0x3B0
- -
- -
-
-
- 0x400
- ECC_VERIFY_R[12] ECC component verify R result register type definition
-
-
-
-
-
- 0x430
- -
- -
-
-
- 0x480
- ECC_IV[12] ECC component IV register type definition
-
-
-
-
-
- 0x4B0
- -
- -
-
-
- 0x600
- ecc_kv_rd_pkey_ctrl Key Vault Read Control Register
-
-
-
-
-
- 0x604
- ecc_kv_rd_pkey_status Key Vault Status Register
-
-
-
-
-
- 0x608
- ecc_kv_rd_seed_ctrl Key Vault Read Control Register
-
-
-
-
-
- 0x60C
- ecc_kv_rd_seed_status Key Vault Status Register
-
-
-
-
-
- 0x610
- ecc_kv_rd_msg_ctrl Key Vault Read Control Register
-
-
-
-
-
- 0x614
- ecc_kv_rd_msg_status Key Vault Status Register
-
-
-
-
-
- 0x618
- ecc_kv_wr_pkey_ctrl Key Vault Write Control Register
-
-
-
-
-
- 0x61C
- ecc_kv_wr_pkey_status Key Vault Status Register
-
-
-
-
-
- 0x620
- -
- -
-
-
- 0x800
- intr_block_rf Interrupt Register Block
-
-
-
-
-
-
-
Interrupt Status Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of each interrupt event.
-Sticky, level assertion, write-1-to-clear.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_sts
-
-
-
-
Command Done Interrupt status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Status Aggregation Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0xc
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of any interrupt event
-of a given type. E.g. Notifications and Errors may drive
-to two separate interrupt registers. There may be
-multiple sources of Notifications or Errors that are
-aggregated into a single interrupt pin for that
-respective type. That pin feeds through this register
-in order to apply a global enablement of that interrupt
-event type.
-Nonsticky assertion.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
agg_sts
-
-
-
-
Interrupt Event Aggregation status bit
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x100
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
ECC component signature S register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x380
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
12 32-bit registers storing the signature S of the message.
-These registers is read by ECC user after signing operation,
-or be set before verifying operation.
-The signature S should be in [1 : q-1] while q is the group
-order of the Secp384r1 curve.
-These registers are located at ECC_base_address +
-0x0000_0380 to 0x0000_03AC in big-endian representation.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
SIGN_S
-
-
-
-
Signature S field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Per-Type Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event type that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_en
-
-
-
-
Global enable bit for all events of type 'Notification'
-
-
-
error_en
-
-
-
-
Global enable bit for all events of type 'Error'
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x200
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x200
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
Key Vault Status Register
-
-
-
- Absolute Address:
- Base Offset: 0x61c
- Size: 0x4
-
-
-
Description
-
-
Reports the Key Vault flow status for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ERROR - Key Vault Error
-
-
-
-
Indicates the error status of a key vault flow
-
-
- enum kv_error_e
-
-
- SUCCESS
- 0x0
- Key Vault flow was successful
-
- KV_READ_FAIL
- 0x1
- Key Vault Read flow failed
-
- KV_WRITE_FAIL
- 0x2
- Key Vault Write flow failed
-
-
-
-
VALID
-
-
-
-
Key Vault flow is done
-
-
-
READY
-
-
-
-
Key Vault control is ready for use
-
-
-
fuse_owner_pk_hash
-
-
-
- Absolute Address:
- Base Offset: 0x284
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
Owner PK hash Fuse.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
hash
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
ECC component public key (x) register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x200
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
12 32-bit registers storing the x coordinate of public key.
-These registers is read by ECC user after keygen operation,
-or be set before verifying operation.
-The public key x should be in [1 : p-1] while p is the prime
-number of the Secp384r1 curve.
-These registers are located at ECC_base_address +
-0x0000_0200 to 0x0000_022C in big-endian representation.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
PUBKEY_X
-
-
-
-
Public key x field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
soc_ifc_reg
-
-
-
- Absolute Address:
- Base Offset: 0x30030000
- Size: 0xa24
-
-
-
Description
-
-
Address map for SoC Interface Block architectural registers and fuse space
-
-
-
Contents
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x100
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
Key Vault Status Register
-
-
-
- Absolute Address:
- Base Offset: 0x614
- Size: 0x4
-
-
-
Description
-
-
Reports the Key Vault flow status for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ERROR - Key Vault Error
-
-
-
-
Indicates the error status of a key vault flow
-
-
- enum kv_error_e
-
-
- SUCCESS
- 0x0
- Key Vault flow was successful
-
- KV_READ_FAIL
- 0x1
- Key Vault Read flow failed
-
- KV_WRITE_FAIL
- 0x2
- Key Vault Write flow failed
-
-
-
-
VALID
-
-
-
-
Key Vault flow is done
-
-
-
READY
-
-
-
-
Key Vault control is ready for use
-
-
-
Interrupt Status Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of each interrupt event.
-Sticky, level assertion, write-1-to-clear.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_sts
-
-
-
-
Command Done status bit
-
-
-
SHA512 component block register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x80
- Size: 0x4
- Array Dimensions: [32]
- Array Stride: +0x4
- Total Size: 0x80
-
-
-
Description
-
-
32 32-bit registers storing the 1024-bit padded input.
-These registers are located at SHA512_base_address +
-0x0000_0080 to 0x0000_00FC in big-endian representation.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
BLOCK
-
-
-
-
Input message block field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
sha512_acc_csr
-
-
-
- Absolute Address:
- Base Offset: 0x30021000
- Size: 0xa14
-
-
-
Description
-
-
Address map for SHA Acceleration Block Register Space
-
-
-
Contents
-
-
-
- Offset
- Identifier
- Name
-
-
- 0x000
- LOCK SHA Accelerator Lock
-
-
-
-
-
- 0x004
- USER SHA Accelerator User
-
-
-
-
-
- 0x008
- MODE SHA Accelerator Mode
-
-
-
-
-
- 0x00C
- START_ADDRESS SHA Accelerator Data Start Address
-
-
-
-
-
- 0x010
- DLEN SHA Accelerator Data Length
-
-
-
-
-
- 0x014
- DATAIN SHA Accelerator Data In
-
-
-
-
-
- 0x018
- EXECUTE SHA Accelerator Execute
-
-
-
-
-
- 0x01C
- STATUS SHA Accelerator Status
-
-
-
-
-
- 0x020
- DIGEST[16] SHA Accelerator Digest
-
-
-
-
-
- 0x060
- CONTROL SHA Accelerator Control
-
-
-
-
-
- 0x064
- -
- -
-
-
- 0x800
- intr_block_rf Interrupt Register Block
-
-
-
-
-
-
-
HMAC384 component version register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
- Array Dimensions: [2]
- Array Stride: +0x4
- Total Size: 0x8
-
-
-
Description
-
-
Two 32-bit read-only registers repereseting of the version
-of HMAC384 component. These registers are located at
-HMAC384_base_address + 0x0000_0008 and 0x0000_000C addresses.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
VERSION
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x180
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x108
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x21c
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
Reset Reason
-
-
-
- Absolute Address:
- Base Offset: 0x40
- Size: 0x4
-
-
-
Description
-
-
Indicates to ROM the originating cause for the PC to be reset to 0.
-Only reset during cold-boot (sticky).
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
WARM_RESET
-
-
-
-
warm reset has been executed
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
FW_UPD_RESET
-
-
-
-
FW update reset has been executed
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
ECC component public key (y) register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x280
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
12 32-bit registers storing the y coordinate of public key.
-These registers is read by ECC user after keygen operation,
-or be set before verifying operation.
-The public key y should be in [1 : p-1] while p is the prime
-number of the Secp384r1 curve.
-These registers are located at ECC_base_address +
-0x0000_0280 to 0x0000_02AC in big-endian representation.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
PUBKEY_Y
-
-
-
-
Public key y field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
fuse_anti_rollback_disable
-
-
-
- Absolute Address:
- Base Offset: 0x2c8
- Size: 0x4
-
-
-
Description
-
-
Anti Rollback Disable Fuse.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
dis
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x208
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
doe_reg
-
-
-
- Absolute Address:
- Base Offset: 0x10000000
- Size: 0xa14
-
-
-
Description
-
-
address maps for DOE register space
-
-
-
Contents
-
-
-
- Offset
- Identifier
- Name
-
-
- 0x000
- DOE_IV[4] DOE component IV register
-
-
-
-
-
- 0x010
- DOE_CTRL DOE Command control register
-
-
-
-
-
- 0x014
- DOE_STATUS DOE component status register
-
-
-
-
-
- 0x018
- -
- -
-
-
- 0x800
- intr_block_rf Interrupt Register Block
-
-
-
-
-
-
-
pv_reg
-
-
-
- Absolute Address:
- Base Offset: 0x1001a000
- Size: 0xc00
-
-
-
Description
-
-
address map for pcrvault
-
-
-
Contents
-
-
-
-
Interrupt Status Aggregation Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of any interrupt event
-of a given type. E.g. Notifications and Errors may drive
-to two separate interrupt registers. There may be
-multiple sources of Notifications or Errors that are
-aggregated into a single interrupt pin for that
-respective type. That pin feeds through this register
-in order to apply a global enablement of that interrupt
-event type.
-Nonsticky assertion.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
agg_sts
-
-
-
-
Interrupt Event Aggregation status bit
-
-
-
ECC component control register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
One 3-bit register to set the type of ECC operations.
-bit #[1:0]: This can be:
- 00 for NONE
- 01 for KEYGEN
- 10 for SIGNING
- 11 for VERIFYING
-bit #2: Zeroize all internal registers after ECC process, to avoid SCA leakage.
-This register is located at ECC_base_address + 0x0000_0010.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ZEROIZE
-
-
-
-
Zeroize all internal registers
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
CTRL
-
-
-
-
Control command field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x100
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
Per-Type Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event type that may produce an interrupt.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_en
-
-
-
-
Global enable bit for all events of type 'Notification'
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
error_en
-
-
-
-
Global enable bit for all events of type 'Error'
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x114
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x10c
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
Per-Event Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x4
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error3_en
-
-
-
-
Enable bit for Event 3
-
-
-
error2_en
-
-
-
-
Enable bit for Event 2
-
-
-
error1_en
-
-
-
-
Enable bit for Event 1
-
-
-
error0_en
-
-
-
-
Enable bit for Event 0
-
-
-
Generic Input Wires
-
-
-
- Absolute Address:
- Base Offset: 0xc0
- Size: 0x4
- Array Dimensions: [2]
- Array Stride: +0x4
- Total Size: 0x8
-
-
-
Description
-
-
Generic input wires connected to SoC interface.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
generic_wires
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Status Aggregation Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0xc
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of any interrupt event
-of a given type. E.g. Notifications and Errors may drive
-to two separate interrupt registers. There may be
-multiple sources of Notifications or Errors that are
-aggregated into a single interrupt pin for that
-respective type. That pin feeds through this register
-in order to apply a global enablement of that interrupt
-event type.
-Nonsticky assertion.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
agg_sts
-
-
-
-
Interrupt Event Aggregation status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
PCR_CTRL
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
- Array Dimensions: [32]
- Array Stride: +0x4
- Total Size: 0x80
-
-
-
Description
-
-
Controls for each pcr entry
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
rsvd1
-
-
-
-
-
rsvd0
-
-
-
-
-
clear
-
-
-
-
Clear the data stored in this entry. Lock will prevent this clear.
-
-
-
lock
-
-
-
-
Lock the PCR from being cleared
-
-
- Property
- Value
-
-
- resetsignal^.^.hard_reset_b
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x20c
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x100
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.hard_reset_b
-
-
-
-
-
-
BOOTFSM GO
-
-
-
- Absolute Address:
- Base Offset: 0xb4
- Size: 0x4
-
-
-
Description
-
-
Indicates that the BootFSM can continue to execute to bring the uController out of reset
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
GO
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Key Vault Status Register
-
-
-
- Absolute Address:
- Base Offset: 0x604
- Size: 0x4
-
-
-
Description
-
-
Reports the Key Vault flow status for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ERROR - Key Vault Error
-
-
-
-
Indicates the error status of a key vault flow
-
-
- enum kv_error_e
-
-
- SUCCESS
- 0x0
- Key Vault flow was successful
-
- KV_READ_FAIL
- 0x1
- Key Vault Read flow failed
-
- KV_WRITE_FAIL
- 0x2
- Key Vault Write flow failed
-
-
-
-
VALID
-
-
-
-
Key Vault flow is done
-
-
-
READY
-
-
-
-
Key Vault control is ready for use
-
-
-
Key Vault Read Control Register
-
-
-
- Absolute Address:
- Base Offset: 0x600
- Size: 0x4
-
-
-
Description
-
-
Controls the Key Vault read access for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
rsvd
-
-
-
-
-
pcr_hash_extend
-
-
-
-
Requested entry is a PCR. This is used only for SHA to hash extend, it's NOP in all other engines
-
-
-
read_entry
-
-
-
-
Key Vault entry to retrieve the read data from for the engine
-
-
-
read_en
-
-
-
-
Indicates that the read data is to come from the key vault.
-Setting this bit to 1 initiates copying of data from the key vault.
-
-
-
hmac_reg
-
-
-
- Absolute Address:
- Base Offset: 0x10010000
- Size: 0xa14
-
-
-
Description
-
-
address maps for HMAC384 register space
-
-
-
Contents
-
-
-
-
NonStickyDataVaultCtrl
-
-
-
- Absolute Address:
- Base Offset: 0x208
- Size: 0x4
- Array Dimensions: [10]
- Array Stride: +0x4
- Total Size: 0x28
-
-
-
Description
-
-
Controls for the Non-Sticky Data Vault Entries
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
lock_entry
-
-
-
-
Lock writes to this entry. Writes will be suppressed when locked.
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Mailbox User
-
-
-
- Absolute Address:
- Base Offset: 0x4
- Size: 0x4
-
-
-
Description
-
-
Stores the user that locked the mailbox
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
user
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
sha512_reg
-
-
-
- Absolute Address:
- Base Offset: 0x10020000
- Size: 0xa14
-
-
-
Description
-
-
address maps for SHA512 register space
-
-
-
Contents
-
-
-
- Offset
- Identifier
- Name
-
-
- 0x000
- SHA512_NAME[2] SHA512 component name register type definition
-
-
-
-
-
- 0x008
- SHA512_VERSION[2] SHA512 component version register type definition
-
-
-
-
-
- 0x010
- SHA512_CTRL SHA512 component control register type definition
-
-
-
-
-
- 0x014
- -
- -
-
-
- 0x018
- SHA512_STATUS SHA512 component status register type definition
-
-
-
-
-
- 0x01C
- -
- -
-
-
- 0x080
- SHA512_BLOCK[32] SHA512 component block register type definition
-
-
-
-
-
- 0x100
- SHA512_DIGEST[16] SHA512 component digest register type definition
-
-
-
-
-
- 0x140
- -
- -
-
-
- 0x600
- SHA512_VAULT_RD_CTRL Key Vault Read Control Register
-
-
-
-
-
- 0x604
- SHA512_VAULT_RD_STATUS Key Vault Status Register
-
-
-
-
-
- 0x608
- SHA512_KV_WR_CTRL Key Vault Write Control Register
-
-
-
-
-
- 0x60C
- SHA512_KV_WR_STATUS Key Vault Status Register
-
-
-
-
-
- 0x610
- SHA512_GEN_PCR_HASH Generate PCR Hash
-
-
-
-
-
- 0x614
- -
- -
-
-
- 0x800
- intr_block_rf Interrupt Register Block
-
-
-
-
-
-
-
Interrupt Status Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x14
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of each interrupt event.
-Sticky, level assertion, write-1-to-clear.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error3_sts
-
-
-
-
Interrupt Event 3 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
error2_sts
-
-
-
-
Interrupt Event 2 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
error1_sts
-
-
-
-
Interrupt Event 1 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
error0_sts
-
-
-
-
Interrupt Event 0 status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x10c
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
ECC component signature R register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x300
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
12 32-bit registers storing the signature R of the message.
-These registers is read by ECC user after signing operation,
-or be set before verifying operation.
-The signature R should be in [1 : q-1] while q is the group
-order of the Secp384r1 curve.
-Based on RFC6979, If R turns out to be zero, a new nonce (by changing
-the private key or the message) should be selected and R computed
-again (this is an utterly improbable occurrence).
-These registers are located at ECC_base_address +
-0x0000_0300 to 0x0000_032C in big-endian representation.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
SIGN_R
-
-
-
-
Signature R field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Hardware Error Fatal
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
-
-
-
Description
-
-
Indicates fatal hardware error.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_code
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x108
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
Mailbox Execute
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
-
-
-
Description
-
-
Mailbox execute register indicates to receiver that the sender is done
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
execute
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
ECC component hashed message register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x100
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
12 32-bit registers storing the hash of the message respect
-to SHA384 algorithm.
-The hashed message can be any 384-bit value in [0 : 2^384-1].
-These registers are located at ECC_base_address +
-0x0000_0100 to 0x0000_012C in big-endian representation.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
MSG
-
-
-
-
Input message field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x104
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Status Aggregation Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of any interrupt event
-of a given type. E.g. Notifications and Errors may drive
-to two separate interrupt registers. There may be
-multiple sources of Notifications or Errors that are
-aggregated into a single interrupt pin for that
-respective type. That pin feeds through this register
-in order to apply a global enablement of that interrupt
-event type.
-Nonsticky assertion.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
agg_sts
-
-
-
-
Interrupt Event Aggregation status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
Mailbox Data Length
-
-
-
- Absolute Address:
- Base Offset: 0xc
- Size: 0x4
-
-
-
Description
-
-
Data length for mailbox access in bytes
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
length
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x208
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
SHA256 component version register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
- Array Dimensions: [2]
- Array Stride: +0x4
- Total Size: 0x8
-
-
-
Description
-
-
Two 32-bit read-only registers repereseting of the version
-of SHA256 component. These registers are located at
-SHA256_base_address + 0x0000_0008 and 0x0000_000C addresses.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
VERSION
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x208
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
ECC component status register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
-
-
-
Description
-
-
One 2-bit register including the following flags:
-bit #0: READY : Indicates if the core is ready to take
- a control command and process the block.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
VALID
-
-
-
-
Status valid bit
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
READY
-
-
-
-
Status ready bit
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Valid User for TRNG
-
-
-
- Absolute Address:
- Base Offset: 0x70
- Size: 0x4
-
-
-
Description
-
-
Valid PAUSER attributes for TRNG on SoC APB Interface.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
PAUSER
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x204
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x108
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x10c
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
SHA Accelerator Status
-
-
-
- Absolute Address:
- Base Offset: 0x1c
- Size: 0x4
-
-
-
Description
-
-
Status register indicating when the requested function is complete
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
VALID
-
-
-
-
Valid bit, indicating that the digest is complete
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Trigger Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x1c
- Size: 0x4
-
-
-
Description
-
-
Single bit for each interrupt event allows SW to manually
-trigger occurrence of that event. Upon SW write, the bit
-will pulse for 1 cycle then clear to 0.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error3_trig
-
-
-
-
Interrupt Trigger 3 bit
-
-
-
error2_trig
-
-
-
-
Interrupt Trigger 2 bit
-
-
-
error1_trig
-
-
-
-
Interrupt Trigger 1 bit
-
-
-
error0_trig
-
-
-
-
Interrupt Trigger 0 bit
-
-
-
fuse_fmc_key_manifest_svn
-
-
-
- Absolute Address:
- Base Offset: 0x2b4
- Size: 0x4
-
-
-
Description
-
-
FMC Security Version Number.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
svn
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Mailbox Force Unlock
-
-
-
- Absolute Address:
- Base Offset: 0x20
- Size: 0x4
-
-
-
Description
-
-
Capability for uC only to force unlock the mailbox.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
unlock
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Key Vault Write Control Register
-
-
-
- Absolute Address:
- Base Offset: 0x608
- Size: 0x4
-
-
-
Description
-
-
Controls the Key Vault write access for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
rsvd
-
-
-
-
-
ecc_msg_dest_valid
-
-
-
-
ECC MSG is a valid destination
-
-
-
ecc_seed_dest_valid
-
-
-
-
ECC SEED is a valid destination
-
-
-
ecc_pkey_dest_valid
-
-
-
-
ECC PKEY is a valid destination
-
-
-
sha_block_dest_valid
-
-
-
-
SHA BLOCK is a valid destination
-
-
-
hmac_block_dest_valid
-
-
-
-
HMAC BLOCK is a valid destination
-
-
-
hmac_key_dest_valid
-
-
-
-
HMAC KEY is a valid destination
-
-
-
write_entry
-
-
-
-
Key Vault entry to store the result
-
-
-
write_en
-
-
-
-
Indicates that the result is to be stored in the key vault.
-Setting this bit to 1 will copy the result to the keyvault when it is ready.
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x104
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
Mailbox DataIn
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
Data in register, write the next data to mailbox
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
datain
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Key Vault Status Register
-
-
-
- Absolute Address:
- Base Offset: 0x60c
- Size: 0x4
-
-
-
Description
-
-
Reports the Key Vault flow status for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ERROR - Key Vault Error
-
-
-
-
Indicates the error status of a key vault flow
-
-
- enum kv_error_e
-
-
- SUCCESS
- 0x0
- Key Vault flow was successful
-
- KV_READ_FAIL
- 0x1
- Key Vault Read flow failed
-
- KV_WRITE_FAIL
- 0x2
- Key Vault Write flow failed
-
-
-
-
VALID
-
-
-
-
Key Vault flow is done
-
-
-
READY
-
-
-
-
Key Vault control is ready for use
-
-
-
SHA Accelerator Lock
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
-
-
-
Description
-
-
SHA lock register for SHA access, reading 0 will set the lock, Write 1 to clear the lock
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
LOCK
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Per-Type Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event type that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_en
-
-
-
-
Global enable bit for all events of type 'Notification'
-
-
-
error_en
-
-
-
-
Global enable bit for all events of type 'Error'
-
-
-
fuse_key_manifest_pk_hash
-
-
-
- Absolute Address:
- Base Offset: 0x250
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
Key Manifest PK hash Fuse.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
hash
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Key Vault Write Control Register
-
-
-
- Absolute Address:
- Base Offset: 0x618
- Size: 0x4
-
-
-
Description
-
-
Controls the Key Vault write access for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
rsvd
-
-
-
-
-
ecc_msg_dest_valid
-
-
-
-
ECC MSG is a valid destination
-
-
-
ecc_seed_dest_valid
-
-
-
-
ECC SEED is a valid destination
-
-
-
ecc_pkey_dest_valid
-
-
-
-
ECC PKEY is a valid destination
-
-
-
sha_block_dest_valid
-
-
-
-
SHA BLOCK is a valid destination
-
-
-
hmac_block_dest_valid
-
-
-
-
HMAC BLOCK is a valid destination
-
-
-
hmac_key_dest_valid
-
-
-
-
HMAC KEY is a valid destination
-
-
-
write_entry
-
-
-
-
Key Vault entry to store the result
-
-
-
write_en
-
-
-
-
Indicates that the result is to be stored in the key vault.
-Setting this bit to 1 will copy the result to the keyvault when it is ready.
-
-
-
ICCM Lock
-
-
-
- Absolute Address:
- Base Offset: 0x620
- Size: 0x4
-
-
-
Description
-
-
Lock feature gates writes to the ICCM. When lock is set to
-1, writes are blocked. When cleared to 0, writes allowed.
-Write-once, meaning only a reset can clear it once set to 1.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
lock
-
-
-
-
Lock bit gates writes to ICCM. Write 1 to set - cannot be cleared by SW.
-
-
-
SHA512 component name register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
- Array Dimensions: [2]
- Array Stride: +0x4
- Total Size: 0x8
-
-
-
Description
-
-
Two 32-bit read-only registers repereseting of the name
-of SHA512 component. These registers are located at
-SHA512_base_address + 0x0000_0000 and 0x0000_0004 addresses.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
NAME
-
-
-
-
-
StickyLockableScratchRegCtrl
-
-
-
- Absolute Address:
- Base Offset: 0x480
- Size: 0x4
- Array Dimensions: [8]
- Array Stride: +0x4
- Total Size: 0x20
-
-
-
Description
-
-
Sticky Scratch Register Controls
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
lock_entry
-
-
-
-
Lock writes to the Scratch registers. Writes will be suppressed when locked.
-
-
- Property
- Value
-
-
- resetsignal^.^.hard_reset_b
-
-
-
-
-
-
SHA512 component version register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
- Array Dimensions: [2]
- Array Stride: +0x4
- Total Size: 0x8
-
-
-
Description
-
-
Two 32-bit read-only registers repereseting of the version
-of SHA512 component. These registers are located at
-SHA512_base_address + 0x0000_0008 and 0x0000_000C addresses.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
VERSION
-
-
-
-
-
SHA512 component digest register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x100
- Size: 0x4
- Array Dimensions: [16]
- Array Stride: +0x4
- Total Size: 0x40
-
-
-
Description
-
-
16 32-bit registers storing the 512-bit digest output.
-These registers are located at SHA512_base_address +
-0x0000_0100 to 0x0000_013C in big-endian representation.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
DIGEST
-
-
-
-
Output digest field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Interrupt Status Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of each interrupt event.
-Sticky, level assertion, write-1-to-clear.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_sts
-
-
-
-
Command Done Interrupt status bit
-
-
-
SHA256 component digest register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x100
- Size: 0x4
- Array Dimensions: [8]
- Array Stride: +0x4
- Total Size: 0x20
-
-
-
Description
-
-
8 32-bit registers storing the 256-bit digest output.
-These registers are located at SHA256_base_address +
-0x0000_0100 to 0x0000_011C in big-endian representation.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
DIGEST
-
-
-
-
Output digest field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x20c
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
StickyLockableScratchReg
-
-
-
- Absolute Address:
- Base Offset: 0x4a0
- Size: 0x4
- Array Dimensions: [8]
- Array Stride: +0x4
- Total Size: 0x20
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
data
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.hard_reset_b
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x104
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x10c
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.error_reset_b
-
-
-
-
-
-
Per-Type Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event type that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_en
-
-
-
-
Global enable bit for all events of type 'Notification'
-
-
-
error_en
-
-
-
-
Global enable bit for all events of type 'Error'
-
-
-
Field Entropy
-
-
-
- Absolute Address:
- Base Offset: 0x230
- Size: 0x4
- Array Dimensions: [8]
- Array Stride: +0x4
- Total Size: 0x20
-
-
-
Description
-
-
Obfuscated Field Entropy.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
seed
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Valid User for TRNG PAUSER Lock
-
-
-
- Absolute Address:
- Base Offset: 0x74
- Size: 0x4
-
-
-
Description
-
-
Valid PAUSER attributes for requests from SoC APB Interface.
-Each bit corresponds to locking the associated VALID_PAUSER register.
-Caliptra FW RW access for survivability but cannot unlock once locked
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
LOCK
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x200
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x204
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
Interrupt Status Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of each interrupt event.
-Sticky, level assertion, write-1-to-clear.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_sts
-
-
-
-
Command Done Interrupt status bit
-
-
-
Interrupt Trigger Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x1c
- Size: 0x4
-
-
-
Description
-
-
Single bit for each interrupt event allows SW to manually
-trigger occurrence of that event. Upon SW write, the bit
-will pulse for 1 cycle then clear to 0.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error3_trig
-
-
-
-
Interrupt Trigger 3 bit
-
-
-
error2_trig
-
-
-
-
Interrupt Trigger 2 bit
-
-
-
error1_trig
-
-
-
-
Interrupt Trigger 1 bit
-
-
-
error0_trig
-
-
-
-
Interrupt Trigger 0 bit
-
-
-
Interrupt Register Block
-
-
-
- Absolute Address:
- Base Offset: 0x800
- Size: 0x214
-
-
-
Description
-
-
Set of registers to implement interrupt functionality
-
-
-
Contents
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x180
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
-
HMAC384 component key register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x40
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
12 32-bit registers storing the 384-bit key.
-These registers are located at HMAC384_base_address +
-0x0000_0040 to 0x0000_006C in big-endian representation.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
KEY
-
-
-
-
Input HMAC384 key field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x20c
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
SHA Accelerator Data In
-
-
-
- Absolute Address:
- Base Offset: 0x14
- Size: 0x4
-
-
-
Description
-
-
Data in register for SHA Streaming function
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
DATAIN
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Per-Event Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x4
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error3_en
-
-
-
-
Enable bit for Event 3
-
-
-
error2_en
-
-
-
-
Enable bit for Event 2
-
-
-
error1_en
-
-
-
-
Enable bit for Event 1
-
-
-
error0_en
-
-
-
-
Enable bit for Event 0
-
-
-
mbox_csr
-
-
-
- Absolute Address:
- Base Offset: 0x30020000
- Size: 0x24
-
-
-
Description
-
-
address maps for mbox register space
-
-
-
Contents
-
-
-
- Offset
- Identifier
- Name
-
-
- 0x00
- mbox_lock Mailbox Lock
-
-
-
-
-
- 0x04
- mbox_user Mailbox User
-
-
-
-
-
- 0x08
- mbox_cmd Mailbox Command
-
-
-
-
-
- 0x0C
- mbox_dlen Mailbox Data Length
-
-
-
-
-
- 0x10
- mbox_datain Mailbox DataIn
-
-
-
-
-
- 0x14
- mbox_dataout Mailbox DataOut
-
-
-
-
-
- 0x18
- mbox_execute Mailbox Execute
-
-
-
-
-
- 0x1C
- mbox_status Mailbox Status
-
-
-
-
-
- 0x20
- mbox_unlock Mailbox Force Unlock
-
-
-
-
-
-
-
Per-Event Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_en
-
-
-
-
Enable bit for Command Done Interrupt
-
-
-
Per-Event Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x4
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error3_en
-
-
-
-
Enable bit for Event 3
-
-
-
error2_en
-
-
-
-
Enable bit for Event 2
-
-
-
error1_en
-
-
-
-
Enable bit for Event 1
-
-
-
error0_en
-
-
-
-
Enable bit for Event 0
-
-
-
ECC component version register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
- Array Dimensions: [2]
- Array Stride: +0x4
- Total Size: 0x8
-
-
-
Description
-
-
Two 32-bit read-only registers repereseting of the version
-of ECC component. These registers are located at
-ECC_base_address + 0x0000_0008 and 0x0000_000C addresses.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
VERSION
-
-
-
-
-
Interrupt Trigger Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x1c
- Size: 0x4
-
-
-
Description
-
-
Single bit for each interrupt event allows SW to manually
-trigger occurrence of that event. Upon SW write, the bit
-will pulse for 1 cycle then clear to 0.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_internal_trig
-
-
-
-
Internal Errors trigger bit
-
-
-
Mailbox Lock
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
-
-
-
Description
-
-
Mailbox lock register for mailbox access, reading 0 will set the lock
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
lock
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
sha256_reg
-
-
-
- Absolute Address:
- Base Offset: 0x10028000
- Size: 0xa14
-
-
-
Description
-
-
address maps for SHA256 register space
-
-
-
Contents
-
-
-
- Offset
- Identifier
- Name
-
-
- 0x000
- SHA256_NAME[2] SHA256 component name register type definition
-
-
-
-
-
- 0x008
- SHA256_VERSION[2] SHA256 component version register type definition
-
-
-
-
-
- 0x010
- SHA256_CTRL SHA256 component control register type definition
-
-
-
-
-
- 0x014
- -
- -
-
-
- 0x018
- SHA256_STATUS SHA256 component status register type definition
-
-
-
-
-
- 0x01C
- -
- -
-
-
- 0x080
- SHA256_BLOCK[16] SHA256 component block register type definition
-
-
-
-
-
- 0x0C0
- -
- -
-
-
- 0x100
- SHA256_DIGEST[8] SHA256 component digest register type definition
-
-
-
-
-
- 0x120
- -
- -
-
-
- 0x800
- intr_block_rf Interrupt Register Block
-
-
-
-
-
-
-
Key Vault Status Register
-
-
-
- Absolute Address:
- Base Offset: 0x604
- Size: 0x4
-
-
-
Description
-
-
Reports the Key Vault flow status for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ERROR - Key Vault Error
-
-
-
-
Indicates the error status of a key vault flow
-
-
- enum kv_error_e
-
-
- SUCCESS
- 0x0
- Key Vault flow was successful
-
- KV_READ_FAIL
- 0x1
- Key Vault Read flow failed
-
- KV_WRITE_FAIL
- 0x2
- Key Vault Write flow failed
-
-
-
-
VALID
-
-
-
-
Key Vault flow is done
-
-
-
READY
-
-
-
-
Key Vault control is ready for use
-
-
-
Per-Event Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_en
-
-
-
-
Enable bit for Command Done Interrupt
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x180
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x180
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
-
SHA512 component control register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
One 5-bit register including the following flags:
-bit #0: INIT : Trigs the SHA512 core to start the
- processing for the first padded message block.
-bit #1: NEXT: Trigs the SHA512 core to start the
- processing for the remining padded message block.
-bit #3-2: MODE : Indicates the SHA512 core to set dynamically
- the type of hashing algorithm. This can be:
- 00 for SHA512/224
- 01 for SHA512/256
- 10 for SHA384
- 11 for SHA512
-bit #4: Zeroize all internal registers after SHA process, to avoid SCA leakage.
-This register is located at SHA512_base_address + 0x0000_0010
-After each software write, hardware will erase the register.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
LAST
-
-
-
-
Indicates last iteration for hash extend function.
-Result of this INIT or NEXT cycle will be written back to PCR
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
ZEROIZE
-
-
-
-
Zeroize all internal registers
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
MODE
-
-
-
-
Control mode command bits
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
NEXT
-
-
-
-
Control next command bit
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
INIT
-
-
-
-
Control init command bit
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Interrupt Status Aggregation Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0xc
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of any interrupt event
-of a given type. E.g. Notifications and Errors may drive
-to two separate interrupt registers. There may be
-multiple sources of Notifications or Errors that are
-aggregated into a single interrupt pin for that
-respective type. That pin feeds through this register
-in order to apply a global enablement of that interrupt
-event type.
-Nonsticky assertion.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
agg_sts
-
-
-
-
Interrupt Event Aggregation status bit
-
-
-
Hardware Error Encoding
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
Encoded error value for hardware errors.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_code
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
SHA Accelerator Control
-
-
-
- Absolute Address:
- Base Offset: 0x60
- Size: 0x4
-
-
-
Description
-
-
SHA Accelerator control flows.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ZEROIZE
-
-
-
-
Zeroize all internal registers
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Firmware Extended Error Information
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
- Array Dimensions: [8]
- Array Stride: +0x4
- Total Size: 0x20
-
-
-
Description
-
-
Firmware Extended Error information for firmware errors.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_info
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Status Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x14
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of each interrupt event.
-Sticky, level assertion, write-1-to-clear.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_mbox_ecc_unc_sts
-
-
-
-
Mailbox ECC Double-bit Error (uncorrectable) status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
error_iccm_blocked_sts
-
-
-
-
ICCM access blocked by lock status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
error_bad_fuse_sts
-
-
-
-
Bad Fuse received from SoC status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
error_cmd_fail_sts
-
-
-
-
Failed Commands status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
error_inv_dev_sts
-
-
-
-
Invalid Device in Pauser field status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
error_internal_sts
-
-
-
-
Internal Errors status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Status Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x14
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of each interrupt event.
-Sticky, level assertion, write-1-to-clear.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_internal_sts
-
-
-
-
Internal Errors status bit
-
-
- Property
- Value
-
-
- resetsignal^.^.^.hard_reset_b
-
-
-
-
-
-
Key Vault Read Control Register
-
-
-
- Absolute Address:
- Base Offset: 0x600
- Size: 0x4
-
-
-
Description
-
-
Controls the Key Vault read access for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
rsvd
-
-
-
-
-
pcr_hash_extend
-
-
-
-
Requested entry is a PCR. This is used only for SHA to hash extend, it's NOP in all other engines
-
-
-
read_entry
-
-
-
-
Key Vault entry to retrieve the read data from for the engine
-
-
-
read_en
-
-
-
-
Indicates that the read data is to come from the key vault.
-Setting this bit to 1 initiates copying of data from the key vault.
-
-
-
Interrupt Register Block
-
-
-
- Absolute Address:
- Base Offset: 0x800
- Size: 0x214
-
-
-
Description
-
-
Set of registers to implement interrupt functionality
-
-
-
Contents
-
-
-
-
NONSTICKY_DATA_VAULT_ENTRY
-
-
-
- Absolute Address:
- Base Offset: 0x230
- Size: 0x4
- Array Dimensions: [10, 12]
- Array Stride: +0x4
- Total Size: 0x1e0
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
data
-
-
-
-
DataVault Entry
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Key Vault Status Register
-
-
-
- Absolute Address:
- Base Offset: 0x60c
- Size: 0x4
-
-
-
Description
-
-
Reports the Key Vault flow status for this engine
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ERROR - Key Vault Error
-
-
-
-
Indicates the error status of a key vault flow
-
-
- enum kv_error_e
-
-
- SUCCESS
- 0x0
- Key Vault flow was successful
-
- KV_READ_FAIL
- 0x1
- Key Vault Read flow failed
-
- KV_WRITE_FAIL
- 0x2
- Key Vault Write flow failed
-
-
-
-
VALID
-
-
-
-
Key Vault flow is done
-
-
-
READY
-
-
-
-
Key Vault control is ready for use
-
-
-
De-Obfuscation Key
-
-
-
- Absolute Address:
- Base Offset: 0x600
- Size: 0x4
- Array Dimensions: [8]
- Array Stride: +0x4
- Total Size: 0x20
-
-
-
Description
-
-
Stored De-Obfuscation key, not accessible by software.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
-
Global Caliptra Clk gating enable
-
-
-
- Absolute Address:
- Base Offset: 0xbc
- Size: 0x4
-
-
-
Description
-
-
Control register to enable or disable all of the caliptra clk gating. Default is 0 (disabled).
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
clk_gating_en
-
-
-
-
Clk gating enable
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Per-Event Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_en
-
-
-
-
Enable bit for Command Done Interrupt
-
-
-
Interrupt Trigger Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x20
- Size: 0x4
-
-
-
Description
-
-
Single bit for each interrupt event allows SW to manually
-trigger occurrence of that event. Upon SW write, the bit
-will pulse for 1 cycle then clear to 0.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_trig
-
-
-
-
Command Done trigger bit
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x20c
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x110
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x10c
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
Interrupt Status Aggregation Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of any interrupt event
-of a given type. E.g. Notifications and Errors may drive
-to two separate interrupt registers. There may be
-multiple sources of Notifications or Errors that are
-aggregated into a single interrupt pin for that
-respective type. That pin feeds through this register
-in order to apply a global enablement of that interrupt
-event type.
-Nonsticky assertion.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
agg_sts
-
-
-
-
Interrupt Event Aggregation status bit
-
-
-
Interrupt Status Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
-
-
-
Description
-
-
Single bit indicating occurrence of each interrupt event.
-Sticky, level assertion, write-1-to-clear.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_sts
-
-
-
-
Command Done Interrupt status bit
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x180
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
-
NonStickyLockableScratchRegCtrl
-
-
-
- Absolute Address:
- Base Offset: 0x410
- Size: 0x4
- Array Dimensions: [10]
- Array Stride: +0x4
- Total Size: 0x28
-
-
-
Description
-
-
Non-Sticky Scratch Register Controls
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
lock_entry
-
-
-
-
Lock writes to the Scratch registers. Writes will be suppressed when locked.
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Interrupt Event Count Incrementor
-
-
-
- Absolute Address:
- Base Offset: 0x214
- Size: 0x4
-
-
-
Description
-
-
Trigger the event counter to increment based on observing
-the rising edge of an interrupt event input from the
-Hardware. The same input signal that causes an interrupt
-event to be set (sticky) also causes this signal to pulse
-for 1 clock cycle, resulting in the event counter
-incrementing by 1 for every interrupt event.
-This is implemented as a down-counter (1-bit) that will
-decrement immediately on being set - resulting in a pulse
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
pulse
-
-
-
-
Pulse mirrors interrupt event occurrence
-
-
-
Interrupt Trigger Register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x1c
- Size: 0x4
-
-
-
Description
-
-
Single bit for each interrupt event allows SW to manually
-trigger occurrence of that event. Upon SW write, the bit
-will pulse for 1 cycle then clear to 0.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_mbox_ecc_unc_trig
-
-
-
-
Mailbox ECC Double-bit Error (uncorrectable) trigger bit
-
-
-
error_iccm_blocked_trig
-
-
-
-
ICCM access blocked by lock trigger bit
-
-
-
error_bad_fuse_trig
-
-
-
-
Bad Fuse received from SoC trigger bit
-
-
-
error_cmd_fail_trig
-
-
-
-
Failed Commands trigger bit
-
-
-
error_inv_dev_trig
-
-
-
-
Invalid Device in Pauser field trigger bit
-
-
-
error_internal_trig
-
-
-
-
Internal Errors trigger bit
-
-
-
CLEAR_SECRETS
-
-
-
- Absolute Address:
- Base Offset: 0xc00
- Size: 0x4
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
sel_debug_value
-
-
-
-
Selects between debug value 0 or 1 parameter to write to keyvault
-
-
-
wr_debug_values
-
-
-
-
Fill the keyvault with debug values
-
-
-
Per-Type Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event type that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_en
-
-
-
-
Global enable bit for all events of type 'Notification'
-
-
-
error_en
-
-
-
-
Global enable bit for all events of type 'Error'
-
-
-
Per-Event Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
notif_cmd_done_en
-
-
-
-
Enable bit for Command Done Interrupt
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_rst_b
-
-
-
-
-
-
NonStickyGenericScratchReg
-
-
-
- Absolute Address:
- Base Offset: 0x460
- Size: 0x4
- Array Dimensions: [8]
- Array Stride: +0x4
- Total Size: 0x20
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
data
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Interrupt Event Counter
-
-
-
- Absolute Address:
- Base Offset: 0x108
- Size: 0x4
-
-
-
Description
-
-
Provides statistics about the number of events that have
-occurred.
-Will not overflow ('incrsaturate').
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cnt
-
-
-
-
Count field
-
-
- Property
- Value
-
-
- resetsignal^.^.^.cptra_pwrgood
-
-
-
-
-
-
ECC component private key register type definition
-
-
-
- Absolute Address:
- Base Offset: 0x180
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
12 32-bit registers storing the private key. These registers
-is read by ECC user after keygen operation, or be set before
-signing operation.
-The private key should be in [1 : q-1] while q is the group
-order of the Secp384r1 curve.
-These registers are located at ECC_base_address +
-0x0000_0180 to 0x0000_01AC in big-endian representation.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
PRIVKEY
-
-
-
-
Private key field
-
-
- Property
- Value
-
-
- resetsignal^.^.reset_b
-
-
-
-
-
-
Per-Event Interrupt Enable Register
-
-
-
- Absolute Address:
- Base Offset: 0x4
- Size: 0x4
-
-
-
Description
-
-
Dedicated register with one bit for each event that may produce an interrupt.
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_mbox_ecc_unc_en
-
-
-
-
Enable bit for Mailbox ECC Double-bit Error (uncorrectable)
-
-
-
error_iccm_blocked_en
-
-
-
-
Enable bit for ICCM access blocked by lock
-
-
-
error_bad_fuse_en
-
-
-
-
Enable bit for Bad Fuse received from SoC
-
-
-
error_cmd_fail_en
-
-
-
-
Enable bit for Failed Commands
-
-
-
error_inv_dev_en
-
-
-
-
Enable bit for Invalid Device in Pauser field
-
-
-
error_internal_en
-
-
-
-
Enable bit for Internal Errors
-
-
.
- * and can be redistributed under the terms of GNU GPL v3 .
- * and can be redistributed under the terms of GNU GPL v3
-
-
-
-
-
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deleted file mode 100644
index 4f5aa88f3..000000000
--- a/src/integration/docs/caliptra_reg_html/fonts/FontAwesome/fa-solid-900.svg
+++ /dev/null
@@ -1,2444 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/src/integration/docs/caliptra_reg_html/fonts/FontAwesome/fa-solid-900.ttf b/src/integration/docs/caliptra_reg_html/fonts/FontAwesome/fa-solid-900.ttf
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diff --git a/src/integration/docs/caliptra_reg_html/fonts/RobotoSlab/roboto-slab-v7-regular.woff2 b/src/integration/docs/caliptra_reg_html/fonts/RobotoSlab/roboto-slab-v7-regular.woff2
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diff --git a/src/integration/docs/caliptra_reg_html/index.html b/src/integration/docs/caliptra_reg_html/index.html
deleted file mode 100644
index 85d01413b..000000000
--- a/src/integration/docs/caliptra_reg_html/index.html
+++ /dev/null
@@ -1,124 +0,0 @@
-
-
-
-
- clp Reference
-
-
-
-
Keyboard Shortcuts
-
- / Open Search
- Ctrl +/ Open Search relative to current page
- Ctrl +[ and Ctrl +] Cycle through path index editors
- Ctrl +\ Navigate to parent page
-
-
-
-
-
-
\ No newline at end of file
diff --git a/src/integration/docs/caliptra_reg_html/js/address_search.js b/src/integration/docs/caliptra_reg_html/js/address_search.js
deleted file mode 100644
index eeb4d112a..000000000
--- a/src/integration/docs/caliptra_reg_html/js/address_search.js
+++ /dev/null
@@ -1,33 +0,0 @@
-// This file is part of PeakRDL-html .
-// and can be redistributed under the terms of GNU GPL v3 .
-// and can be redistributed under the terms of GNU GPL v3 = 2){
- for(var j=0; j {
- this.#bucket_files[bidx] = data;
- });
- return awaitable;
- }
-
-
- static async #get_matches(keywords, abortSignal){
-
- // Find locations of matching keywords
- var match_list = [];
- var match_hashtable = {};
- var itercount = 0;
- for(var i=0; i {
- return a.compare_rank_to(b);
- });
-
- return match_list;
- }
-
-
- static async #fetch_match_preview_text(match){
- return fetch_page_content(match.page_id).then(text => {
- var dp = new DOMParser();
- var doc = dp.parseFromString(text, "text/html");
-
- // Prune out the element that is most relevant to the content match
- var el;
- var el_id;
- if(match.is_field) {
- if(match.is_name) {
- // use field's row in table, since it contains the name
- el_id = match.field_name;
- } else {
- // field's description block
- el_id = "_Content." + match.field_name + ".desc";
- }
- } else {
- // Not a field
- if(match.is_name) {
- // Use page title
- el_id = "_Content.name";
- } else {
- // main description block
- el_id = "_Content.desc";
- }
- }
- var el = doc.getElementById(el_id);
-
- // strip HTML tags
- text = el.textContent;
-
- // Reduce excess whitespace
- text = text.replace(/\s+/g, " ");
-
- // Mark all keywords in content
- var keywords = Array.from(new Set([...match.full_match_keywords, ...match.partial_match_keywords]));
- var regex = new RegExp("(?:\\b|_)(" + keywords.join("|") + ")", "ig");
- var marked_text = "";
- var prev_idx = 0;
- for (const m of text.matchAll(regex)) {
- var m_idx = m.index;
-
- // advance match past underscore if it is in match
- if(text[m_idx] == "_") m_idx += 1;
-
- // Pass through prior segment
- if(prev_idx < m_idx) {
- var unmarked_segment = text.slice(prev_idx, m_idx);
- if(unmarked_segment.length > this.#PREVIEW_MAX_RUN_LENGTH) {
- // shorten the segment
- if(marked_text == ""){
- // is first
- unmarked_segment = this.#shorten_text_first(unmarked_segment);
- } else {
- // is middle
- unmarked_segment = this.#shorten_text_middle(unmarked_segment);
- }
- }
- marked_text += unmarked_segment;
- }
-
- // highlight segment
- marked_text += "" + m[1] + " ";
- prev_idx = m_idx + m[1].length;
- }
-
- if(prev_idx < text.length){
- // pass through last unmarked segment
- var unmarked_segment = text.slice(prev_idx, text.index);
- if(unmarked_segment.length > this.#PREVIEW_MAX_RUN_LENGTH) {
- // shorten the segment
- unmarked_segment = this.#shorten_text_last(unmarked_segment);
- }
- marked_text += unmarked_segment;
- }
-
- return marked_text;
- });
- }
-
- static #shorten_text_first(text){
- var L = this.#PREVIEW_MAX_RUN_LENGTH;
- return "\u22ef" + text.slice(text.length - L, text.length);
- }
-
- static #shorten_text_middle(text){
- var L = this.#PREVIEW_MAX_RUN_LENGTH;
- return text.slice(0, L/2) + "\u22ef \u22ef" + text.slice(text.length - L/2, text.length);
- }
-
- static #shorten_text_last(text){
- var L = this.#PREVIEW_MAX_RUN_LENGTH;
- return text.slice(0, L) + "\u22ef";
- }
-}
-
-
-class ContentSearchMatch {
- constructor(location_entry){
- this.full_match_keywords = new Set();
- this.partial_match_keywords = new Set();
- this.page_id = location_entry[0];
-
- var location_code = location_entry[1];
- this.is_name = Boolean(location_code & 0x1);
- this.is_enum = Boolean(location_code & 0x4);
- this.is_field = Boolean(location_code & 0x2);
- if(this.is_field){
- var field_idx = (location_code >> 3);
- this.field_name = RAL.get_node(this.page_id).fields[field_idx].name;
- } else {
- this.field_name = null;
- }
- }
-
- get_location_key(){
- // unique key that represents mergeable match location
- return String([this.page_id, this.field_name]);
- }
-
- get_matched_keywords(){
- return new Set([...this.full_match_keywords, ...this.partial_match_keywords]);
- }
-
- compare_rank_to(other){
- // +1: other has higher rank than this
- // -1: other has lower rank than this
- // 0: Other is the same rank
- var this_merged_keywords = this.get_matched_keywords();
- var other_merged_keywords = other.get_matched_keywords();
-
- // Total number of matching keywords is most important
- if(this_merged_keywords.size < other_merged_keywords.size) return 1;
- if(this_merged_keywords.size > other_merged_keywords.size) return -1;
-
- // then whichever has more full matches
- if(this.full_match_keywords.size < other.full_match_keywords.size) return 1;
- if(this.full_match_keywords.size > other.full_match_keywords.size) return -1;
-
- // then whichever has more partial matches
- if(this.partial_match_keywords.size < other.partial_match_keywords.size) return 1;
- if(this.partial_match_keywords.size > other.partial_match_keywords.size) return -1;
-
- return 0;
- }
-}
diff --git a/src/integration/docs/caliptra_reg_html/js/field_testers.js b/src/integration/docs/caliptra_reg_html/js/field_testers.js
deleted file mode 100644
index 4418cd96a..000000000
--- a/src/integration/docs/caliptra_reg_html/js/field_testers.js
+++ /dev/null
@@ -1,213 +0,0 @@
-// This file is part of PeakRDL-html .
-// and can be redistributed under the terms of GNU GPL v3 > lsb;
- var mask = (1n << (msb - lsb + 1n)) - 1n;
- value = value & mask;
- var el = document.getElementById("_FieldValueTester" + node.fields[idx].name);
- el.value = format_field_value(idx, value);
- el.classList.remove("invalid");
-
- if("encode" in RAL.get_node(CurrentID).fields[idx]) {
- var el = document.getElementById("_FieldValueEnumTester" + node.fields[idx].name);
- el.value = "0x" + value.toString(16);
- }
-}
-
-function format_field_value(idx, value) {
- if(RAL.get_node(CurrentID).fields[idx].disp == "D"){
- return(value.toString());
- } else {
- return("0x" + value.toString(16));
- }
-}
-
-function update_field_enum_visibility(idx){
- var node = RAL.get_node(CurrentID);
-
- if(!("encode" in node.fields[idx])) return;
-
- var d = node.fields[idx].disp;
- var enum_el = document.getElementById("_FieldValueEnumTester" + node.fields[idx].name);
- var txt_el = document.getElementById("_FieldValueTester" + node.fields[idx].name);
- if(d == "E") {
- enum_el.style.display = "inline";
- txt_el.style.display = "none";
- } else {
- enum_el.style.display = "none";
- txt_el.style.display = "inline";
- }
-}
-
-//==============================================================================
-// Events
-//==============================================================================
-
-function onRadixSwitch(el){
- var idx = RAL.lookup_field_idx(el.dataset.name);
- var node = RAL.get_node(CurrentID);
- var d = node.fields[idx].disp;
- if(d == "H") {
- d = "D";
- } else if((d == "D") && ("encode" in node.fields[idx])) {
- d = "E";
- } else {
- d = "H";
- }
-
- el.innerHTML = d;
- node.fields[idx].disp = d;
- update_field_enum_visibility(idx);
- update_field_value_tester(idx);
-}
-
-function onDecodedFieldEnumChange(el) {
- var idx = RAL.lookup_field_idx(el.dataset.name);
- var el2 = document.getElementById("_FieldValueTester" + RAL.get_node(CurrentID).fields[idx].name);
- el2.value = el.value;
- update_reg_value_tester();
- save_reg_state();
-}
-
-function onDecodedFieldInput(el){
- var idx = RAL.lookup_field_idx(el.dataset.name);
- var node = RAL.get_node(CurrentID);
- var msb = BigInt(node.fields[idx].msb);
- var lsb = BigInt(node.fields[idx].lsb);
- var value;
-
- try {
- value = BigInt(el.value);
- } catch(error) {
- value = -1n;
- }
-
- var max_value = 1n << (msb - lsb + 1n);
- if((value < 0) || (value >= max_value)){
- if(!el.classList.contains("invalid")) el.classList.add("invalid");
- return;
- }
- el.classList.remove("invalid");
-
- if("encode" in node.fields[idx]) {
- var el2 = document.getElementById("_FieldValueEnumTester" + node.fields[idx].name);
- el2.value = "0x" + value.toString(16);
- }
- update_reg_value_tester();
- save_reg_state();
-}
-
-function onEncodedRegInput(el){
- var value;
- try {
- value = BigInt(el.value);
- } catch(error) {
- value = -1n;
- }
-
- if(value < 0){
- if(!el.classList.contains("invalid")) el.classList.add("invalid");
- return;
- }
- el.classList.remove("invalid");
- update_field_value_testers();
- save_reg_state();
-}
-
-function onResetRegValue(el){
- reset_field_inputs();
- save_reg_state();
-}
diff --git a/src/integration/docs/caliptra_reg_html/js/index_edit.js b/src/integration/docs/caliptra_reg_html/js/index_edit.js
deleted file mode 100644
index e99f80921..000000000
--- a/src/integration/docs/caliptra_reg_html/js/index_edit.js
+++ /dev/null
@@ -1,162 +0,0 @@
-// This file is part of PeakRDL-html .
-// and can be redistributed under the terms of GNU GPL v3 .
-// and can be redistributed under the terms of GNU GPL v3 Oops! "
- + "Most modern browser's security policies "
- + "prevent this page from loading properly when using the file:// protocol.
"
- + "If possible, host this page on a web server and access using the http:// protocol.
"
-
- + "Alternatives "
- ;
-
- if(platform_is_windows()) {
- html_str +=
- "Use one of the included launcher scripts "
- + ""
- + "In the folder that contains these docs, double-click the launcher for the browser of your choice:"
- + "
"
- + " launcher-windows-chrome.batlauncher-windows-edge.batlauncher-windows-firefox.bat "
- + "These launcher scripts will temporarily disable the security setting so you can view this page locally."
- + ""
- ;
- }
-
- if(platform_is_windows()) {
- html_str +=
- "Python http server "
- + ""
- + "Launch a temporary http server using Python:"
- + "
"
- + " If you haven't already, download and install Python "
- + " "
- + " Press WIN +R and paste the following into the text box:"
- + "
"
- + " "
- + " Click 'Ok' "
- + " Re-open this page via: http://localhost:8000/ "
- + " "
- + ""
- ;
- } else {
- html_str +=
- "Python http server "
- + ""
- + "Launch a temporary http server using Python:"
- + "
"
- + 'python3 -m http.server -d "' + this_dir + '"'
- + " "
- + "Then view via: http://localhost:8000/ "
- + ""
- ;
- }
-
- html_str +=
- "Firefox "
- + ""
- + "Change your Firefox security settings:"
- + "
"
- + " In your address bar, type about:config "
- + " Set security.fileuri.strict_origin_policy to false "
- + " Refresh this page "
- + " "
- + ""
- ;
-
- if(platform_is_windows()) {
- html_str +=
- "Chrome or Edge "
- + ""
- + "
"
- + " Close your current Chrome or Edge browser session completely "
- + " "
- + " Press WIN +R and paste the following into the text box:"
- + "
"
- + " For Microsoft Edge, replace 'chrome.exe' with 'msedge.exe'"
- + " "
- + " Click 'Ok' "
- + " "
- + ""
- ;
- } else {
- html_str +=
- "Chrome "
- + ""
- + "Close your current Chrome session and re-launch it from the command-line using:"
- + "
"
- + "google-chrome --allow-file-access-from-files \\\n"
- + ' "' + window.location.href + '"'
- + " "
- + ""
- ;
- }
-
- var el = document.getElementById("_ContentContainer");
- el.innerHTML = html_str;
-}
-
-function show_incompatibility_nag() {
- var el = document.getElementById("_ContentContainer");
- el.innerHTML
- = "Nope! "
- + "It looks like the browser you are using is not supported.
"
- + "Please use a modern browser such as "
- + "Firefox "
- + " or Chrome .
"
- ;
-}
-
-function test_browser_incompatible() {
- // Test for browser features that absolutely have to exist
- try {
- var url = new URL(window.location.href);
- } catch(error) {
- return true;
- }
- return false;
-}
-
-function update_crumbtrail(){
- var crumb_el = document.getElementById("_Crumbtrail");
- var id = CurrentID;
-
- // Delete old crumbtrail
- while (crumb_el.hasChildNodes()) {
- crumb_el.removeChild(crumb_el.lastChild);
- }
-
- var path_ids = RAL.get_ids_in_path(id);
- var crumb_idx_span_idx = 0;
-
- for(var i=0; i setTimeout(r, 1));
-}
-
-function difference(setA, setB) {
- const _difference = new Set(setA);
- for (const elem of setB) {
- _difference.delete(elem);
- }
- return _difference;
-}
-
-function toBigInt(str) {
- // bigInt doesn't handle large hex strings if they use the 0x prefix
- // Wrap auto-base handling
- str = str.trim().toLowerCase();
- if(str.startsWith("0x")) {
- return(bigInt(str.substring(2), 16));
- } else if(str.startsWith("0o")) {
- return(bigInt(str.substring(2), 8));
- } else if(str.startsWith("0b")) {
- return(bigInt(str.substring(2), 2));
- } else {
- return(bigInt(str));
- }
-}
-
-function page_specific_key(key){
- var url = new URL(window.location.href);
- key = url.origin + url.pathname + "::" + key;
- return key;
-}
-
-//==============================================================================
-// Compatibility Workarounds
-//==============================================================================
-// IE does not support Number.isInteger
-function isPositiveInteger(num) {
- return ((num ^ 0) >>> 0) === num;
-}
-
-// IE does not support .startsWith
-if(!String.prototype.startsWith) {
- String.prototype.startsWith = function(searchString, position) {
- position = position || 0;
- return this.indexOf(searchString, position) === position;
- };
-}
diff --git a/src/integration/docs/caliptra_reg_html/js/nav.js b/src/integration/docs/caliptra_reg_html/js/nav.js
deleted file mode 100644
index e6e37e96a..000000000
--- a/src/integration/docs/caliptra_reg_html/js/nav.js
+++ /dev/null
@@ -1,209 +0,0 @@
-// This file is part of PeakRDL-html .
-// and can be redistributed under the terms of GNU GPL v3 .
-// and can be redistributed under the terms of GNU GPL v3 = this.#MAX_RESULTS) {
- break;
- }
- }
- }
-
- static #test_path(path, keywords){
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- var text_segments = [];
- var start = 0;
-
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d=a("./shape"),e=a("./utils"),f=function(a,b){this._pathTemplate=b.vertical?"M {center},100 L {center},0":"M 0,{center} L 100,{center}",d.apply(this,arguments)};f.prototype=new d,f.prototype.constructor=f,f.prototype._initializeSvg=function(a,b){var c=b.vertical?"0 0 "+b.strokeWidth+" 100":"0 0 100 "+b.strokeWidth;a.setAttribute("viewBox",c),a.setAttribute("preserveAspectRatio","none")},f.prototype._pathString=function(a){return e.render(this._pathTemplate,{center:a.strokeWidth/2})},f.prototype._trailString=function(a){return this._pathString(a)},b.exports=f},{"./shape":7,"./utils":9}],4:[function(a,b,c){b.exports={Line:a("./line"),Circle:a("./circle"),SemiCircle:a("./semicircle"),Square:a("./square"),Path:a("./path"),Shape:a("./shape"),utils:a("./utils")}},{"./circle":2,"./line":3,"./path":5,"./semicircle":6,"./shape":7,"./square":8,"./utils":9}],5:[function(a,b,c){var d=a("shifty"),e=a("./utils"),f=d.Tweenable,g={easeIn:"easeInCubic",easeOut:"easeOutCubic",easeInOut:"easeInOutCubic"},h=function a(b,c){if(!(this instanceof a))throw new Error("Constructor was called without new keyword");c=e.extend({delay:0,duration:800,easing:"linear",from:{},to:{},step:function(){}},c);var d;d=e.isString(b)?document.querySelector(b):b,this.path=d,this._opts=c,this._tweenable=null;var f=this.path.getTotalLength();this.path.style.strokeDasharray=f+" "+f,this.set(0)};h.prototype.value=function(){var a=this._getComputedDashOffset(),b=this.path.getTotalLength(),c=1-a/b;return parseFloat(c.toFixed(6),10)},h.prototype.set=function(a){this.stop(),this.path.style.strokeDashoffset=this._progressToOffset(a);var b=this._opts.step;if(e.isFunction(b)){var c=this._easing(this._opts.easing);b(this._calculateTo(a,c),this._opts.shape||this,this._opts.attachment)}},h.prototype.stop=function(){this._stopTween(),this.path.style.strokeDashoffset=this._getComputedDashOffset()},h.prototype.animate=function(a,b,c){b=b||{},e.isFunction(b)&&(c=b,b={});var d=e.extend({},b),g=e.extend({},this._opts);b=e.extend(g,b);var h=this._easing(b.easing),i=this._resolveFromAndTo(a,h,d);this.stop(),this.path.getBoundingClientRect();var j=this._getComputedDashOffset(),k=this._progressToOffset(a),l=this;this._tweenable=new f,this._tweenable.tween({from:e.extend({offset:j},i.from),to:e.extend({offset:k},i.to),duration:b.duration,delay:b.delay,easing:h,step:function(a){l.path.style.strokeDashoffset=a.offset;var c=b.shape||l;b.step(a,c,b.attachment)}}).then(function(a){e.isFunction(c)&&c()}).catch(function(a){throw console.error("Error in tweening:",a),a})},h.prototype._getComputedDashOffset=function(){var a=window.getComputedStyle(this.path,null);return parseFloat(a.getPropertyValue("stroke-dashoffset"),10)},h.prototype._progressToOffset=function(a){var b=this.path.getTotalLength();return b-a*b},h.prototype._resolveFromAndTo=function(a,b,c){return c.from&&c.to?{from:c.from,to:c.to}:{from:this._calculateFrom(b),to:this._calculateTo(a,b)}},h.prototype._calculateFrom=function(a){return d.interpolate(this._opts.from,this._opts.to,this.value(),a)},h.prototype._calculateTo=function(a,b){return d.interpolate(this._opts.from,this._opts.to,a,b)},h.prototype._stopTween=function(){null!==this._tweenable&&(this._tweenable.stop(!0),this._tweenable=null)},h.prototype._easing=function(a){return g.hasOwnProperty(a)?g[a]:a},b.exports=h},{"./utils":9,shifty:1}],6:[function(a,b,c){var d=a("./shape"),e=a("./circle"),f=a("./utils"),g=function(a,b){this._pathTemplate="M 50,50 m -{radius},0 a {radius},{radius} 0 1 1 {2radius},0",this.containerAspectRatio=2,d.apply(this,arguments)};g.prototype=new d,g.prototype.constructor=g,g.prototype._initializeSvg=function(a,b){a.setAttribute("viewBox","0 0 100 50")},g.prototype._initializeTextContainer=function(a,b,c){a.text.style&&(c.style.top="auto",c.style.bottom="0",a.text.alignToBottom?f.setStyle(c,"transform","translate(-50%, 0)"):f.setStyle(c,"transform","translate(-50%, 50%)"))},g.prototype._pathString=e.prototype._pathString,g.prototype._trailString=e.prototype._trailString,b.exports=g},{"./circle":2,"./shape":7,"./utils":9}],7:[function(a,b,c){var d=a("./path"),e=a("./utils"),f="Object is destroyed",g=function a(b,c){if(!(this instanceof a))throw new Error("Constructor was called without new keyword");if(0!==arguments.length){this._opts=e.extend({color:"#555",strokeWidth:1,trailColor:null,trailWidth:null,fill:null,text:{style:{color:null,position:"absolute",left:"50%",top:"50%",padding:0,margin:0,transform:{prefix:!0,value:"translate(-50%, -50%)"}},autoStyleContainer:!0,alignToBottom:!0,value:null,className:"progressbar-text"},svgStyle:{display:"block",width:"100%"},warnings:!1},c,!0),e.isObject(c)&&void 0!==c.svgStyle&&(this._opts.svgStyle=c.svgStyle),e.isObject(c)&&e.isObject(c.text)&&void 0!==c.text.style&&(this._opts.text.style=c.text.style);var f,g=this._createSvgView(this._opts);if(!(f=e.isString(b)?document.querySelector(b):b))throw new Error("Container does not exist: "+b);this._container=f,this._container.appendChild(g.svg),this._opts.warnings&&this._warnContainerAspectRatio(this._container),this._opts.svgStyle&&e.setStyles(g.svg,this._opts.svgStyle),this.svg=g.svg,this.path=g.path,this.trail=g.trail,this.text=null;var h=e.extend({attachment:void 0,shape:this},this._opts);this._progressPath=new d(g.path,h),e.isObject(this._opts.text)&&null!==this._opts.text.value&&this.setText(this._opts.text.value)}};g.prototype.animate=function(a,b,c){if(null===this._progressPath)throw new Error(f);this._progressPath.animate(a,b,c)},g.prototype.stop=function(){if(null===this._progressPath)throw new Error(f);void 0!==this._progressPath&&this._progressPath.stop()},g.prototype.pause=function(){if(null===this._progressPath)throw new Error(f);void 0!==this._progressPath&&this._progressPath._tweenable&&this._progressPath._tweenable.pause()},g.prototype.resume=function(){if(null===this._progressPath)throw new Error(f);void 0!==this._progressPath&&this._progressPath._tweenable&&this._progressPath._tweenable.resume()},g.prototype.destroy=function(){if(null===this._progressPath)throw new Error(f);this.stop(),this.svg.parentNode.removeChild(this.svg),this.svg=null,this.path=null,this.trail=null,this._progressPath=null,null!==this.text&&(this.text.parentNode.removeChild(this.text),this.text=null)},g.prototype.set=function(a){if(null===this._progressPath)throw new Error(f);this._progressPath.set(a)},g.prototype.value=function(){if(null===this._progressPath)throw new Error(f);return void 0===this._progressPath?0:this._progressPath.value()},g.prototype.setText=function(a){if(null===this._progressPath)throw new Error(f);null===this.text&&(this.text=this._createTextContainer(this._opts,this._container),this._container.appendChild(this.text)),e.isObject(a)?(e.removeChildren(this.text),this.text.appendChild(a)):this.text.innerHTML=a},g.prototype._createSvgView=function(a){var b=document.createElementNS("http://www.w3.org/2000/svg","svg");this._initializeSvg(b,a);var c=null;(a.trailColor||a.trailWidth)&&(c=this._createTrail(a),b.appendChild(c));var d=this._createPath(a);return b.appendChild(d),{svg:b,path:d,trail:c}},g.prototype._initializeSvg=function(a,b){a.setAttribute("viewBox","0 0 100 100")},g.prototype._createPath=function(a){var b=this._pathString(a);return this._createPathElement(b,a)},g.prototype._createTrail=function(a){var b=this._trailString(a),c=e.extend({},a);return c.trailColor||(c.trailColor="#eee"),c.trailWidth||(c.trailWidth=c.strokeWidth),c.color=c.trailColor,c.strokeWidth=c.trailWidth,c.fill=null,this._createPathElement(b,c)},g.prototype._createPathElement=function(a,b){var c=document.createElementNS("http://www.w3.org/2000/svg","path");return c.setAttribute("d",a),c.setAttribute("stroke",b.color),c.setAttribute("stroke-width",b.strokeWidth),b.fill?c.setAttribute("fill",b.fill):c.setAttribute("fill-opacity","0"),c},g.prototype._createTextContainer=function(a,b){var c=document.createElement("div");c.className=a.text.className;var d=a.text.style;return d&&(a.text.autoStyleContainer&&(b.style.position="relative"),e.setStyles(c,d),d.color||(c.style.color=a.color)),this._initializeTextContainer(a,b,c),c},g.prototype._initializeTextContainer=function(a,b,c){},g.prototype._pathString=function(a){throw new Error("Override this function for each progress bar")},g.prototype._trailString=function(a){throw new Error("Override this function for each progress bar")},g.prototype._warnContainerAspectRatio=function(a){if(this.containerAspectRatio){var b=window.getComputedStyle(a,null),c=parseFloat(b.getPropertyValue("width"),10),d=parseFloat(b.getPropertyValue("height"),10);e.floatEquals(this.containerAspectRatio,c/d)||(console.warn("Incorrect aspect ratio of container","#"+a.id,"detected:",b.getPropertyValue("width")+"(width)","/",b.getPropertyValue("height")+"(height)","=",c/d),console.warn("Aspect ratio of should be",this.containerAspectRatio))}},b.exports=g},{"./path":5,"./utils":9}],8:[function(a,b,c){var d=a("./shape"),e=a("./utils"),f=function(a,b){this._pathTemplate="M 0,{halfOfStrokeWidth} L {width},{halfOfStrokeWidth} L {width},{width} L {halfOfStrokeWidth},{width} L {halfOfStrokeWidth},{strokeWidth}",this._trailTemplate="M {startMargin},{halfOfStrokeWidth} L {width},{halfOfStrokeWidth} L {width},{width} L {halfOfStrokeWidth},{width} L {halfOfStrokeWidth},{halfOfStrokeWidth}",d.apply(this,arguments)};f.prototype=new d,f.prototype.constructor=f,f.prototype._pathString=function(a){var b=100-a.strokeWidth/2;return e.render(this._pathTemplate,{width:b,strokeWidth:a.strokeWidth,halfOfStrokeWidth:a.strokeWidth/2})},f.prototype._trailString=function(a){var b=100-a.strokeWidth/2;return e.render(this._trailTemplate,{width:b,strokeWidth:a.strokeWidth,halfOfStrokeWidth:a.strokeWidth/2,startMargin:a.strokeWidth/2-a.trailWidth/2})},b.exports=f},{"./shape":7,"./utils":9}],9:[function(a,b,c){function d(a,b,c){a=a||{},b=b||{},c=c||!1;for(var e in b)if(b.hasOwnProperty(e)){var f=a[e],g=b[e];c&&l(f)&&l(g)?a[e]=d(f,g,c):a[e]=g}return a}function e(a,b){var c=a;for(var d in b)if(b.hasOwnProperty(d)){var e=b[d],f="\\{"+d+"\\}",g=new RegExp(f,"g");c=c.replace(g,e)}return c}function f(a,b,c){for(var d=a.style,e=0;e.
-// and can be redistributed under the terms of GNU GPL v3 {
- this.#increment_progressbar();
- this.#ral_data_files[idx] = data;
- })
- .catch(e => {
- this.#destroy_progressbar();
- throw new Error("fetch failed");
- });
- return awaitable;
- }
-
- static #progress_points = 0;
- static #progressbar = null;
- static #init_progressbar(){
- this.#progressbar = new ProgressBar.Circle("#_ProgressBar", {
- strokeWidth: 10, // forces extra padding
- trailWidth: 3,
- text: {
- value: "Loading..."
- }
- });
-
- if(N_RAL_FILES == 1){
- // Only one object to load. animate progress as stand-in.
- this.#progressbar.animate(1, {duration:400});
- }
- }
- static #increment_progressbar(){
- this.#progress_points++;
- this.#progressbar.set(this.#progress_points / N_RAL_FILES);
- if(this.#progress_points == N_RAL_FILES) {
- this.#destroy_progressbar();
- }
- }
-
- static #destroy_progressbar(){
- this.#progressbar.destroy();
- this.#progressbar = null;
- }
-
- static get_node(id){
- var file_idx = Math.floor(id / N_RAL_NODES_PER_FILE);
- var idx = id % N_RAL_NODES_PER_FILE;
- var node = this.#ral_data_files[file_idx][idx];
- this.#expand_bigint(node);
- return node;
- }
-
- static #expand_bigint(node){
- // Check if RAL entry has been converted yet
- if(typeof node.offset !== 'string') return;
-
- // Needs conversion from base-16 string --> BigInt object
- node.offset = BigInt("0x" + node.offset);
- node.size = BigInt("0x" + node.size);
- if('stride' in node) node.stride = BigInt("0x" + node.stride);
-
- if(RAL.is_register_node(node)) {
- for(var i=0; i= segment_idxs[0].length){
- sanitized_idxs.push(0);
- } else {
- sanitized_idxs.push(Math.min(segment_idxs[0][dim], this.get_node(id).dims[dim]-1));
- }
- }
- segment_idxs[0] = sanitized_idxs;
- } else {
- if(segment_idxs[0].length != 0) segment_idxs[0] = [];
- }
-
- // Validate the path and find the end ID
- for(var i=1; i= segment_idxs[i].length){
- sanitized_idxs.push(0);
- } else {
- sanitized_idxs.push(Math.min(segment_idxs[i][dim], this.get_node(id).dims[dim]-1));
- }
- }
- segment_idxs[i] = sanitized_idxs;
- } else {
- if(segment_idxs[i].length != 0) segment_idxs[i] = [];
- }
- }
-
- return([id, segment_idxs]);
- }
-
- static apply_idx_stack(id, idx_stack){
- // Applies the given index stack onto the RAL
- // Assumes the indexes are valid
- for(var i=idx_stack.length-1; i>=0; i--){
- if(idx_stack[i].length){
- this.get_node(id).idxs = idx_stack[i];
- }
- id = this.get_node(id).parent;
- }
- }
-
- static get_path(id, idx_stack, show_idx){
- if(typeof idx_stack === "undefined") idx_stack = null;
- if(typeof show_idx === "undefined") show_idx = true;
-
- // Get string representation of the hierarchical path
- if(show_idx && (idx_stack == null)){
- idx_stack = this.get_current_idx_stack(id);
- }
- var ids = this.get_ids_in_path(id);
- var pathparts = [];
- for(var i=0; i= (this.get_node(id).offset + this.get_total_size(id))) return(null);
-
- while(iter_count < 100){
- iter_count++;
- // addr is definitely inside this node
-
- // Adjust addr to be relative to this node
- addr = addr - this.get_node(id).offset;
-
- // Determine index stack entry for this node
- if(this.is_array(id)){
- var idxs = [];
-
- // First check if address lands between sparse array entries
- if((addr % this.get_node(id).stride) >= this.get_node(id).size) {
- // missed! Give up and just return the parent node
- if(this.get_node(id).parent == null){
- return(null);
- }else{
- return([this.get_node(id).parent, idx_stack]);
- }
- }
-
- // index of the flattened array
- var flat_idx = Number(addr / this.get_node(id).stride);
-
- // Re-construct dimensions
- for(var dim=this.get_node(id).dims.length-1; dim>=0; dim--){
- var idx;
- idx = flat_idx % this.get_node(id).dims[dim];
- flat_idx = Math.floor(flat_idx / this.get_node(id).dims[dim]);
- idxs.unshift(idx);
- }
- idx_stack.push(idxs);
-
- // Adjust addr offset to be relative to this index
- addr = addr % this.get_node(id).stride;
- } else {
- idx_stack.push([]);
- }
-
- // Search this node's children to see which child 'addr' is in
- var found_match = false;
- for(var i=0; i= this.get_node(child).offset) && (addr < (this.get_node(child).offset + this.get_total_size(child)))){
- // hit!
- id = child;
- found_match = true;
- break;
- }
- }
- if(!found_match){
- // No further match. Current node is the result
- return([id, idx_stack]);
- }
- }
-
- // Hit iteration limit. Something is wrong :-(
- throw "Agh! iteration limit reached while looking up by address";
- }
-
- static lookup_field_idx(name) {
- var node = this.get_node(CurrentID);
- for(var i=0; i.
-// and can be redistributed under the terms of GNU GPL v3 tag.
- // text_segments[0] --> not highlighted
- // text_segments[1] --> highlighted
-
- var result_idx = SearchState.results.length;
- var result_el = document.createElement("li");
- result_el.onclick = function() {
- open_search_result(result_idx);
- };
- result_el.onmousemove = function() {
- onSearchResultMousemove(result_idx)
- };
- var path_div_el = document.createElement("div");
- result_el.appendChild(path_div_el);
-
- // Build highlighted path crumbtrail
- for(var i=0; i {
- Sidebar.expand_to_id(result.node_id);
- Sidebar.select_node(result.node_id);
- Sidebar.scroll_into_view(result.node_id);
- refresh_url(url_hash);
- refresh_title();
- refresh_target_scroll();
- });
-}
diff --git a/src/integration/docs/caliptra_reg_html/js/sha1.js b/src/integration/docs/caliptra_reg_html/js/sha1.js
deleted file mode 100644
index 8dd714108..000000000
--- a/src/integration/docs/caliptra_reg_html/js/sha1.js
+++ /dev/null
@@ -1,173 +0,0 @@
-/**
-*
-* Secure Hash Algorithm (SHA1)
-* http://www.webtoolkit.info/
-*
-**/
-
-function SHA1(msg) {
-
- function rotate_left(n,s) {
- var t4 = ( n<>>(32-s));
- return t4;
- };
-
- function lsb_hex(val) {
- var str="";
- var i;
- var vh;
- var vl;
-
- for( i=0; i<=6; i+=2 ) {
- vh = (val>>>(i*4+4))&0x0f;
- vl = (val>>>(i*4))&0x0f;
- str += vh.toString(16) + vl.toString(16);
- }
- return str;
- };
-
- function cvt_hex(val) {
- var str="";
- var i;
- var v;
-
- for( i=7; i>=0; i-- ) {
- v = (val>>>(i*4))&0x0f;
- str += v.toString(16);
- }
- return str;
- };
-
-
- function Utf8Encode(string) {
- string = string.replace(/\r\n/g,"\n");
- var utftext = "";
-
- for (var n = 0; n < string.length; n++) {
-
- var c = string.charCodeAt(n);
-
- if (c < 128) {
- utftext += String.fromCharCode(c);
- }
- else if((c > 127) && (c < 2048)) {
- utftext += String.fromCharCode((c >> 6) | 192);
- utftext += String.fromCharCode((c & 63) | 128);
- }
- else {
- utftext += String.fromCharCode((c >> 12) | 224);
- utftext += String.fromCharCode(((c >> 6) & 63) | 128);
- utftext += String.fromCharCode((c & 63) | 128);
- }
-
- }
-
- return utftext;
- };
-
- var blockstart;
- var i, j;
- var W = new Array(80);
- var H0 = 0x67452301;
- var H1 = 0xEFCDAB89;
- var H2 = 0x98BADCFE;
- var H3 = 0x10325476;
- var H4 = 0xC3D2E1F0;
- var A, B, C, D, E;
- var temp;
-
- msg = Utf8Encode(msg);
-
- var msg_len = msg.length;
-
- var word_array = new Array();
- for( i=0; i>>29 );
- word_array.push( (msg_len<<3)&0x0ffffffff );
-
-
- for ( blockstart=0; blockstart.
-// and can be redistributed under the terms of GNU GPL v3 =0; i--){
- var current_id = id_chain[i];
- var el = this.#get_node_el(current_id);
- if(el == null){
- // doesnt exist. it will get expanded once created
- node_ids_to_expand.unshift(current_id);
- } else {
- // reached node that exists already
- if(el.classList.contains("closed")){
- // .. but it is still closed
- node_ids_to_expand.unshift(current_id);
- }
- break;
- }
- }
-
- // Create missing elements
- for(var i=0; i 0){
- if(el.classList.contains("open")){
- return; // already open
- }
-
- var cdiv;
- cdiv = document.createElement("div");
- cdiv.className = "node-children";
- el.after(cdiv);
-
- for(var i=0; i 0){
- if(el.classList.contains("closed")){
- return; // already closed
- }
- var cdiv = el.nextElementSibling;
- if(cdiv.classList.contains('node-children')){
- cdiv.remove();
- } else {
- console.error("OOPS");
- }
- el.classList.add("closed")
- el.classList.remove("open")
- }
- }
-
- static collapse_all(){
- for(var i=0; i 0){
- // has children
- div.classList.add("closed");
-
- var cdiv;
- cdiv = document.createElement("div");
- cdiv.className = "node-children";
- parent_el.appendChild(cdiv);
- } else {
- // is leaf node
- div.classList.add("leaf");
- }
- }
-
- static select_node(id) {
- // Changes the selected tree node
- var el;
- if(this.#selected_node_id != null){
- el = this.#get_node_el(this.#selected_node_id)
- if(el != null){ // element might have already been deleted
- el.classList.remove("selected");
- }
- }
-
- el = this.#get_node_el(id);
- el.classList.add("selected");
- this.#selected_node_id = id;
- }
-
- static #onResizeMouseDown(e) {
- var sb_el = document.getElementById("_SBContents");
- this.#resizer_old_width = sb_el.getBoundingClientRect().width;
- this.#resizer_start_x = e.clientX;
- window.addEventListener('mousemove', this.#mousemove_cb);
- window.addEventListener('mouseup', this.#mouseup_cb);
- e.preventDefault();
- }
-
- static #onResizeMouseMove(e) {
- var sb_el = document.getElementById("_SBContents");
- var new_width;
- new_width = this.#resizer_old_width + e.clientX - this.#resizer_start_x;
- sb_el.style.width = new_width + "px";
- }
-
- static #onResizeMouseUp(e) {
- window.removeEventListener('mousemove', this.#mousemove_cb);
- window.removeEventListener('mouseup', this.#mouseup_cb);
-
- // remember sidebar width
- var sb_el = document.getElementById("_SBContents");
- localStorage.setItem(page_specific_key("sb_width"), sb_el.style.width);
- }
-
- static show() {
- document.getElementById("_Sidebar").style.display = "flex";
- document.getElementById("_Overlay").style.display = "block";
- }
-
- static hide() {
- document.getElementById("_Sidebar").style.display = "none";
- document.getElementById("_Overlay").style.display = "none";
- }
-
- static scroll_into_view(id){
- var node_el = this.#get_node_el(id);
- var tree_el = document.getElementById("_SBTreeContainer");
-
- var node_rect = node_el.getBoundingClientRect();
- var tree_rect = tree_el.getBoundingClientRect();
-
- if(
- (node_rect.top < tree_rect.top)
- || (node_rect.bottom > tree_rect.bottom)
- || (node_rect.left < tree_rect.left)
- || (node_rect.right > tree_rect.right)
- ) {
- node_el.scrollIntoView({
- block: "nearest",
- inline: "start"
- });
- }
- }
-}
-
-function onClickTreeFold(ev) {
- var el = ev.target.parentNode;
- var id = parseInt(el.dataset.id);
- if(el.classList.contains("leaf")) return;
-
- if(el.classList.contains("closed")){
- // Open this node
- Sidebar.expand_node(id);
-
- // may need to re-select current
- Sidebar.select_node(CurrentID);
- }else{
- // Close this node
- Sidebar.collapse_node(id);
- }
-}
-
-function onClickTreeLink(ev) {
- var el = ev.target.parentNode;
- var id = parseInt(el.dataset.id);
-
- close_search();
- Sidebar.hide();
-
- if(id == CurrentID) return(false);
-
- if(!el.classList.contains("leaf")){
- Sidebar.expand_node(id);
- }
-
- RAL.reset_indexes_to_next(id);
-
- load_page(id).then(() => {
- Sidebar.expand_to_id(id);
- Sidebar.select_node(id);
- refresh_url();
- refresh_title();
- refresh_target_scroll();
- });
- return(false);
-}
-
-function onClickTreeExpandAll() {
- Sidebar.expand_all()
-
- // may need to re-select current
- Sidebar.select_node(CurrentID);
-}
-
-function onClickTreeCollapseAll() {
- Sidebar.collapse_all()
-}
diff --git a/src/integration/docs/caliptra_reg_html/launcher-windows-chrome.bat b/src/integration/docs/caliptra_reg_html/launcher-windows-chrome.bat
deleted file mode 100644
index 09bd64c89..000000000
--- a/src/integration/docs/caliptra_reg_html/launcher-windows-chrome.bat
+++ /dev/null
@@ -1,17 +0,0 @@
-@echo off&setlocal
-
-:: set some convenience variables
-for %%i in ("%~dp0.") do set "this_dir=%%~fi"
-set "docpath=file://%this_dir%\index.html"
-set "launcher_data=%this_dir%\.launcher_data"
-
-:: Launch using Chrome using some special flags:
-:: --allow-file-access-from-files
-:: This flag works around a security policy that prevents dynamic content to be loaded
-:: See this page for more details:
-:: https://developer.mozilla.org/en-US/docs/Web/HTTP/CORS/Errors/CORSRequestNotHttp
-:: --user-data-dir
-:: If chrome already has a session open, then it will re-use that session and the CORS workaround
-:: will not take effect. Forcing chrome to use a temporary alternate user data directory
-:: is a hacky way to force chrome to launch a fresh session
-start "" chrome --allow-file-access-from-files --user-data-dir=%launcher_data%\chrome %docpath%
diff --git a/src/integration/docs/caliptra_reg_html/launcher-windows-edge.bat b/src/integration/docs/caliptra_reg_html/launcher-windows-edge.bat
deleted file mode 100644
index 36cb2a62e..000000000
--- a/src/integration/docs/caliptra_reg_html/launcher-windows-edge.bat
+++ /dev/null
@@ -1,19 +0,0 @@
-@echo off&setlocal
-
-:: set some convenience variables
-for %%i in ("%~dp0.") do set "this_dir=%%~fi"
-set "docpath=file://%this_dir%\index.html"
-set "launcher_data=%this_dir%\.launcher_data"
-
-:: Launch using Edge using some special flags:
-:: --allow-file-access-from-files
-:: This flag works around a security policy that prevents dynamic content to be loaded
-:: See this page for more details:
-:: https://developer.mozilla.org/en-US/docs/Web/HTTP/CORS/Errors/CORSRequestNotHttp
-:: --user-data-dir
-:: If edge already has a session open, then it will re-use that session and the CORS workaround
-:: will not take effect. Forcing edge to use a temporary alternate user data directory
-:: is a hacky way to force edge to launch a fresh session
-:: NOTE: Edge may prompt you with a few "new user" popups the first time, because
-:: the data dir is uninitialized. I could not figure out a clean way to disable this
-start "" msedge --allow-file-access-from-files --user-data-dir=%launcher_data%\msedge %docpath%
diff --git a/src/integration/docs/caliptra_reg_html/launcher-windows-firefox.bat b/src/integration/docs/caliptra_reg_html/launcher-windows-firefox.bat
deleted file mode 100644
index 132f22322..000000000
--- a/src/integration/docs/caliptra_reg_html/launcher-windows-firefox.bat
+++ /dev/null
@@ -1,14 +0,0 @@
-@echo off&setlocal
-
-:: set some convenience variables
-for %%i in ("%~dp0.") do set "this_dir=%%~fi"
-set "docpath=file://%this_dir%\index.html"
-set "launcher_data=%this_dir%\.launcher_data"
-
-:: Launch using Firefox using a pre-configured profile
-:: This profile sets the user preference:
-:: security.fileuri.strict_origin_policy = false
-:: This setting works around a security policy that prevents dynamic content to be loaded
-:: See this page for more details:
-:: https://developer.mozilla.org/en-US/docs/Web/HTTP/CORS/Errors/CORSRequestNotHttp
-start "" firefox -profile %launcher_data%\firefox %docpath%
diff --git a/src/integration/docs/caliptra_reg_html/search/bkt-0.json b/src/integration/docs/caliptra_reg_html/search/bkt-0.json
deleted file mode 100644
index 5d1d2f5d0..000000000
--- a/src/integration/docs/caliptra_reg_html/search/bkt-0.json
+++ /dev/null
@@ -1 +0,0 @@
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diff --git a/src/integration/docs/caliptra_reg_html/search/bkt-1.json b/src/integration/docs/caliptra_reg_html/search/bkt-1.json
deleted file mode 100644
index e0b50e65e..000000000
--- a/src/integration/docs/caliptra_reg_html/search/bkt-1.json
+++ /dev/null
@@ -1 +0,0 @@
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\ No newline at end of file
diff --git a/src/integration/docs/caliptra_reg_html/search/bkt_index.js b/src/integration/docs/caliptra_reg_html/search/bkt_index.js
deleted file mode 100644
index 25ee0a642..000000000
--- a/src/integration/docs/caliptra_reg_html/search/bkt_index.js
+++ /dev/null
@@ -1 +0,0 @@
-var SearchBucketIndex = [233571405,267651219];
\ No newline at end of file
diff --git a/src/soc_ifc/docs/caliptra_top_reg_html/.launcher_data/firefox/user.js b/src/soc_ifc/docs/caliptra_top_reg_html/.launcher_data/firefox/user.js
deleted file mode 100644
index 34b966f00..000000000
--- a/src/soc_ifc/docs/caliptra_top_reg_html/.launcher_data/firefox/user.js
+++ /dev/null
@@ -1,4 +0,0 @@
-user_pref("app.normandy.first_run", false);
-user_pref("toolkit.telemetry.reportingpolicy.firstRun", false);
-
-user_pref("security.fileuri.strict_origin_policy", false);
\ No newline at end of file
diff --git a/src/soc_ifc/docs/caliptra_top_reg_html/content/02262e892a436d03286daa575db308347986e2f5.html b/src/soc_ifc/docs/caliptra_top_reg_html/content/02262e892a436d03286daa575db308347986e2f5.html
deleted file mode 100644
index 459f45c1c..000000000
--- a/src/soc_ifc/docs/caliptra_top_reg_html/content/02262e892a436d03286daa575db308347986e2f5.html
+++ /dev/null
@@ -1,214 +0,0 @@
-
-
-
-
Flow Status
-
-
-
- Absolute Address:
- Base Offset: 0x3c
- Size: 0x4
-
-
-
Description
-
-
Reports the status of the firmware flows.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
mailbox_flow_done
-
-
-
-
Indicates Caliptra is has completed Mailbox Flow.
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
ready_for_fuses
-
-
-
-
Indicates Caliptra is ready for Fuses to be programmed.
-Read-only to both Caliptra and SOC.
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
ready_for_runtime
-
-
-
-
Indicates Caliptra is ready for Runtime Firmware Download
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
ready_for_fw
-
-
-
-
Indicates Caliptra is ready for Firmware Download
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
DEBUG & MANUF SERVICE REG
-
-
-
- Absolute Address:
- Base Offset: 0xb8
- Size: 0x4
-
-
-
Description
-
-
JTAG in debug/manuf mode or SOC can write to this register for ROM/FW defined skips or services; ROM/FW maintains the defintion of these bits.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
DATA
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
BOOTFSM GO
-
-
-
- Absolute Address:
- Base Offset: 0xb4
- Size: 0x4
-
-
-
Description
-
-
Indicates that the BootFSM can continue to execute to bring the uController out of reset
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
GO
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Hardware Error Encoding
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
Encoded error value for hardware errors.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_code
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
SHA Accelerator Execute
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
-
-
-
Description
-
-
For Streaming Function, indicates that the initiator is done streaming.
-For the Mailbox SHA Function, indicates that the SHA can begin execution.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
EXECUTE
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Unique Device Secret
-
-
-
- Absolute Address:
- Base Offset: 0x200
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
Obfuscated UDS.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
seed
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
TRNG Data
-
-
-
- Absolute Address:
- Base Offset: 0x78
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
Storage for the requested TRNG Data.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
DATA
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
SHA Accelerator Data In
-
-
-
- Absolute Address:
- Base Offset: 0x14
- Size: 0x4
-
-
-
Description
-
-
Data in register for SHA Streaming function
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
DATAIN
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Mailbox DataIn
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
Data in register, write the next data to mailbox
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
datain
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Mailbox Execute
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
-
-
-
Description
-
-
Mailbox execute register indicates to receiver that the sender is done
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
execute
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Fuse Write Done
-
-
-
- Absolute Address:
- Base Offset: 0xac
- Size: 0x4
-
-
-
Description
-
-
Writes to fuse registers are completed. After the done bit is set, any subsequent writes to a fuse register will be dropped unless there is a power cycle or a warm reset or caliptra FW allows a write (negotiated through a mailbox command).
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
done
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
fuse_fmc_key_manifest_svn
-
-
-
- Absolute Address:
- Base Offset: 0x2b4
- Size: 0x4
-
-
-
Description
-
-
FMC Security Version Number.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
svn
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
SHA Accelerator Data Length
-
-
-
- Absolute Address:
- Base Offset: 0x10
- Size: 0x4
-
-
-
Description
-
-
The length of data to be processed in bytes.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
LENGTH
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
fuse_key_manifest_pk_hash
-
-
-
- Absolute Address:
- Base Offset: 0x250
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
Key Manifest PK hash Fuse.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
hash
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
fuse_idevid_cert_attr
-
-
-
- Absolute Address:
- Base Offset: 0x2cc
- Size: 0x4
- Array Dimensions: [24]
- Array Stride: +0x4
- Total Size: 0x60
-
-
-
Description
-
-
Manufacturer IEEE IDevID Certificate Gen Attributes.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
cert
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Global Caliptra Clk gating enable
-
-
-
- Absolute Address:
- Base Offset: 0xbc
- Size: 0x4
-
-
-
Description
-
-
Control register to enable or disable all of the caliptra clk gating. Default is 0 (disabled).
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
clk_gating_en
-
-
-
-
Clk gating enable
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
SHA Accelerator Status
-
-
-
- Absolute Address:
- Base Offset: 0x1c
- Size: 0x4
-
-
-
Description
-
-
Status register indicating when the requested function is complete
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
VALID
-
-
-
-
Valid bit, indicating that the digest is complete
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Timer Config
-
-
-
- Absolute Address:
- Base Offset: 0xb0
- Size: 0x4
-
-
-
Description
-
-
Provides the clock period of the system clock.
-Used to standardize the RISC-V Standard MTIME count register.
-Clock Period is indicated as an integer number of picoseconds.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
clk_period
-
-
-
-
Period in (ps)
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Generic Output Wires
-
-
-
- Absolute Address:
- Base Offset: 0xc8
- Size: 0x4
- Array Dimensions: [2]
- Array Stride: +0x4
- Total Size: 0x8
-
-
-
Description
-
-
Generic output wires connected to SoC interface.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
generic_wires
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Reset Reason
-
-
-
- Absolute Address:
- Base Offset: 0x40
- Size: 0x4
-
-
-
Description
-
-
Indicates to ROM the originating cause for the PC to be reset to 0.
-Only reset during cold-boot (sticky).
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
WARM_RESET
-
-
-
-
warm reset has been executed
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
FW_UPD_RESET
-
-
-
-
FW update reset has been executed
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
fuse_key_manifest_pk_hash_mask
-
-
-
- Absolute Address:
- Base Offset: 0x280
- Size: 0x4
-
-
-
Description
-
-
Key Manifest Mask Fuse.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
mask
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
SHA Accelerator Digest
-
-
-
- Absolute Address:
- Base Offset: 0x20
- Size: 0x4
- Array Dimensions: [16]
- Array Stride: +0x4
- Total Size: 0x40
-
-
-
Description
-
-
16 32-bit registers storing the 512-bit digest output in
-big-endian representation.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
DIGEST
-
-
-
-
Output digest field
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
sha512_acc_csr
-
-
-
- Absolute Address:
- Base Offset: 0x30021000
- Size: 0x64
-
-
-
Description
-
-
Address map for SHA Acceleration Block Register Space
-
-
-
Contents
-
-
-
- Offset
- Identifier
- Name
-
-
- 0x00
- LOCK SHA Accelerator Lock
-
-
-
-
-
- 0x04
- USER SHA Accelerator User
-
-
-
-
-
- 0x08
- MODE SHA Accelerator Mode
-
-
-
-
-
- 0x0C
- START_ADDRESS SHA Accelerator Data Start Address
-
-
-
-
-
- 0x10
- DLEN SHA Accelerator Data Length
-
-
-
-
-
- 0x14
- DATAIN SHA Accelerator Data In
-
-
-
-
-
- 0x18
- EXECUTE SHA Accelerator Execute
-
-
-
-
-
- 0x1C
- STATUS SHA Accelerator Status
-
-
-
-
-
- 0x20
- DIGEST[16] SHA Accelerator Digest
-
-
-
-
-
- 0x60
- CONTROL SHA Accelerator Control
-
-
-
-
-
-
-
Valid User for TRNG
-
-
-
- Absolute Address:
- Base Offset: 0x70
- Size: 0x4
-
-
-
Description
-
-
Valid PAUSER attributes for TRNG on SoC APB Interface.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
PAUSER
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Field Entropy
-
-
-
- Absolute Address:
- Base Offset: 0x230
- Size: 0x4
- Array Dimensions: [8]
- Array Stride: +0x4
- Total Size: 0x20
-
-
-
Description
-
-
Obfuscated Field Entropy.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
seed
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Firmware Extended Error Information
-
-
-
- Absolute Address:
- Base Offset: 0x18
- Size: 0x4
- Array Dimensions: [8]
- Array Stride: +0x4
- Total Size: 0x20
-
-
-
Description
-
-
Firmware Extended Error information for firmware errors.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_info
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Mailbox User
-
-
-
- Absolute Address:
- Base Offset: 0x4
- Size: 0x4
-
-
-
Description
-
-
Stores the user that locked the mailbox
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
user
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Mailbox Force Unlock
-
-
-
- Absolute Address:
- Base Offset: 0x20
- Size: 0x4
-
-
-
Description
-
-
Capability for uC only to force unlock the mailbox.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
unlock
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
fuse_runtime_svn
-
-
-
- Absolute Address:
- Base Offset: 0x2b8
- Size: 0x4
- Array Dimensions: [4]
- Array Stride: +0x4
- Total Size: 0x10
-
-
-
Description
-
-
Runtime SVN Fuse.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
svn
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Hardware Error Non-Fatal
-
-
-
- Absolute Address:
- Base Offset: 0x4
- Size: 0x4
-
-
-
Description
-
-
Indicates non-fatal hardware error.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_code
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Mailbox Data Length
-
-
-
- Absolute Address:
- Base Offset: 0xc
- Size: 0x4
-
-
-
Description
-
-
Data length for mailbox access in bytes
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
length
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Firmware Error Encoding
-
-
-
- Absolute Address:
- Base Offset: 0x14
- Size: 0x4
-
-
-
Description
-
-
Encoded error value for firmware errors.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_code
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
SHA Accelerator User
-
-
-
- Absolute Address:
- Base Offset: 0x4
- Size: 0x4
-
-
-
Description
-
-
Stores the user that locked the SHA
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
USER
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
fuse_anti_rollback_disable
-
-
-
- Absolute Address:
- Base Offset: 0x2c8
- Size: 0x4
-
-
-
Description
-
-
Anti Rollback Disable Fuse.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
dis
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
SHA Accelerator Control
-
-
-
- Absolute Address:
- Base Offset: 0x60
- Size: 0x4
-
-
-
Description
-
-
SHA Accelerator control flows.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ZEROIZE
-
-
-
-
Zeroize all internal registers
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
caliptra_top_reg
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x30030340
-
-
-
-
Contents
-
-
-
- Offset
- Identifier
- Name
-
-
- 0x3001FFFF
- -
- -
-
-
- 0x30020000
- mbox_csr -
-
-
-
-
-
- 0x30020024
- -
- -
-
-
- 0x30021000
- sha512_acc_csr -
-
-
-
-
-
- 0x30021064
- -
- -
-
-
- 0x30030000
- generic_and_fuse_reg -
-
-
-
-
-
-
-
Valid User Register Lock
-
-
-
- Absolute Address:
- Base Offset: 0x5c
- Size: 0x4
- Array Dimensions: [5]
- Array Stride: +0x4
- Total Size: 0x14
-
-
-
Description
-
-
Valid PAUSER attributes for requests from SoC APB Interface.
-Each bit corresponds to locking the associated VALID_PAUSER register.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
LOCK
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Firmware Error Non-Fatal
-
-
-
- Absolute Address:
- Base Offset: 0xc
- Size: 0x4
-
-
-
Description
-
-
Indicates non-fatal firmware error.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_code
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
TRNG Status
-
-
-
- Absolute Address:
- Base Offset: 0xa8
- Size: 0x4
-
-
-
Description
-
-
TRNG Status register to indicate request and done
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
DATA_WR_DONE
-
-
-
-
Indicates that the requests TRNG Data is done and stored in the TRNG Data register.
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
DATA_REQ
-
-
-
-
Indicates that the requests TRNG Data is done and stored in the TRNG Data register.
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
SHA Accelerator Mode
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
-
-
-
Description
-
-
Stores the requested mode for the SHA to execute.
-SHA Supports both SHA384 and SHA512 modes of operation.
-SHA Supports streaming mode - SHA is computed on a stream of incoming data to datain register.
- mailbox mode - SHA is computed on LENGTH bytes of data stored in the mailbox from START_ADDRESS.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ENDIAN_TOGGLE - Endianness Toggle for SHA in mailbox mode
-
-
-
-
Default behavior assumes that data in mailbox is little endian,
-When set to 0, data from mailbox will be swizzled from little to big endian at the byte level.
-When set to 1, data from the mailbox will be loaded into SHA as-is.
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
MODE
-
-
-
-
-
- enum sha_cmd_e
-
-
- SHA_STREAM_384
- 0x0
- SHA is in SHA384, streaming mode
-
- SHA_STREAM_512
- 0x1
- SHA is in SHA512, streaming mode
-
- SHA_MBOX_384
- 0x2
- SHA is in SHA384, mailbox mode
-
- SHA_MBOX_512
- 0x3
- SHA is in SHA512, mailbox mode
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
mbox_csr
-
-
-
- Absolute Address:
- Base Offset: 0x30020000
- Size: 0x24
-
-
-
Description
-
-
address maps for mbox register space
-
-
-
Contents
-
-
-
- Offset
- Identifier
- Name
-
-
- 0x00
- mbox_lock Mailbox Lock
-
-
-
-
-
- 0x04
- mbox_user Mailbox User
-
-
-
-
-
- 0x08
- mbox_cmd Mailbox Command
-
-
-
-
-
- 0x0C
- mbox_dlen Mailbox Data Length
-
-
-
-
-
- 0x10
- mbox_datain Mailbox DataIn
-
-
-
-
-
- 0x14
- mbox_dataout Mailbox DataOut
-
-
-
-
-
- 0x18
- mbox_execute Mailbox Execute
-
-
-
-
-
- 0x1C
- mbox_status Mailbox Status
-
-
-
-
-
- 0x20
- mbox_unlock Mailbox Force Unlock
-
-
-
-
-
-
-
fuse_owner_pk_hash
-
-
-
- Absolute Address:
- Base Offset: 0x284
- Size: 0x4
- Array Dimensions: [12]
- Array Stride: +0x4
- Total Size: 0x30
-
-
-
Description
-
-
Owner PK hash Fuse.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
hash
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Firmware Error Fatal
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
-
-
-
Description
-
-
Indicates fatal firmware error.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_code
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
SHA Accelerator Lock
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
-
-
-
Description
-
-
SHA lock register for SHA access, reading 0 will set the lock, Write 1 to clear the lock
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
LOCK
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
generic_and_fuse_reg
-
-
-
- Absolute Address:
- Base Offset: 0x30030000
- Size: 0x340
-
-
-
Description
-
-
Address map for SoC Interface Block architectural registers and fuse space
-
-
-
Contents
-
-
-
-
Valid User for TRNG PAUSER Lock
-
-
-
- Absolute Address:
- Base Offset: 0x74
- Size: 0x4
-
-
-
Description
-
-
Valid PAUSER attributes for requests from SoC APB Interface.
-Each bit corresponds to locking the associated VALID_PAUSER register.
-Caliptra FW RW access for survivability but cannot unlock once locked
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
LOCK
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Valid User Registers
-
-
-
- Absolute Address:
- Base Offset: 0x48
- Size: 0x4
- Array Dimensions: [5]
- Array Stride: +0x4
- Total Size: 0x14
-
-
-
Description
-
-
Valid PAUSER attributes for requests from SoC APB Interface.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
PAUSER
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Hardware Error Fatal
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
-
-
-
Description
-
-
Indicates fatal hardware error.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
error_code
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
fuse_life_cycle
-
-
-
- Absolute Address:
- Base Offset: 0x33c
- Size: 0x4
-
-
-
Description
-
-
Caliptra Boot Media Integrated mode usage only. SOCs that build with a Boot Media Independent profile don’t have to account for these fuses.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
life_cycle
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Generic Input Wires
-
-
-
- Absolute Address:
- Base Offset: 0xc0
- Size: 0x4
- Array Dimensions: [2]
- Array Stride: +0x4
- Total Size: 0x8
-
-
-
Description
-
-
Generic input wires connected to SoC interface.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
generic_wires
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Mailbox Lock
-
-
-
- Absolute Address:
- Base Offset: 0x0
- Size: 0x4
-
-
-
Description
-
-
Mailbox lock register for mailbox access, reading 0 will set the lock
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
lock
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Boot Status
-
-
-
- Absolute Address:
- Base Offset: 0x38
- Size: 0x4
-
-
-
Description
-
-
Reports the boot status.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
status
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
SHA Accelerator Data Start Address
-
-
-
- Absolute Address:
- Base Offset: 0xc
- Size: 0x4
-
-
-
Description
-
-
The start address for FW controlled SHA performed on data stored in the mailbox.
-Start Address must be dword aligned.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
ADDR
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Mailbox Status
-
-
-
- Absolute Address:
- Base Offset: 0x1c
- Size: 0x4
-
-
-
Description
-
-
Status of the mailbox command
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
soc_has_lock - SoC Acquired the Lock
-
-
-
-
Indicates that the current lock was acquired by the SoC
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
mbox_fsm_ps - Mailbox FSM Present State
-
-
-
-
Indicates the present state of the mailbox FSM
-
-
-
- enum mbox_fsm_e
-
-
- MBOX_IDLE
- 0x0
- Mailbox is idle
-
- MBOX_RDY_FOR_CMD
- 0x1
- Mailbox is waiting for command
-
- MBOX_RDY_FOR_DLEN
- 0x3
- Mailbox is waiting for data length
-
- MBOX_RDY_FOR_DATA
- 0x2
- Mailbox is ready for data
-
- MBOX_EXECUTE_UC
- 0x6
- Mailbox has data for uC
-
- MBOX_EXECUTE_SOC
- 0x4
- Mailbox has data for SoC
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
ecc_double_error - Mailbox ECC Double Error
-
-
-
-
Indicates an uncorrectable ECC double-bit error
-was detected while reading dataout.
-Firmware developers are advised to set the command
-status to CMD_FAILURE in response.
-Auto-clears when mbox_execute field is cleared.
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
ecc_single_error - Mailbox ECC Single Error
-
-
-
-
Indicates a correctable ECC single-bit error was
-detected and corrected while reading dataout.
-Auto-clears when mbox_execute field is cleared.
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
status - Mailbox Status
-
-
-
-
Indicates the status of mailbox command
-
-
-
- enum mbox_status_e
-
-
- CMD_BUSY
- 0x0
- Receiver is busy, command is not yet complete.
-
- DATA_READY
- 0x1
- Requested data is ready in the mailbox.
-
- CMD_COMPLETE
- 0x2
- Requested command is complete.
-
- CMD_FAILURE
- 0x3
- The requested command experienced a failure.
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
fuse_idevid_manuf_hsm_id
-
-
-
- Absolute Address:
- Base Offset: 0x32c
- Size: 0x4
- Array Dimensions: [4]
- Array Stride: +0x4
- Total Size: 0x10
-
-
-
Description
-
-
Manufacturer IDEVID Manufacturer’s HSM identifier (this is used to find the certificate chain from the boot media)
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
hsm_id
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_pwrgood
-
-
-
-
-
-
Security State
-
-
-
- Absolute Address:
- Base Offset: 0x44
- Size: 0x4
-
-
-
Description
-
-
Indicates current hardware security state.
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
rsvd
-
-
-
-
Reserved field
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
scan_mode
-
-
-
-
scan mode signal observed at caliptra interface - only for debug mode as its used to flush assets -
-when truly in scan mode, everything will be BROKEN for functional reads!
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
debug_locked
-
-
-
-
Debug Locked
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
device_lifecycle
-
-
-
-
Device Lifecycle
-
-
- enum device_lifecycle_e
-
-
- DEVICE_UNPROVISIONED
- 0x0
- Unprovisioned
-
- DEVICE_MANUFACTURING
- 0x1
- Manufacturing
-
- DEVICE_PRODUCTION
- 0x3
- Production
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Mailbox Command
-
-
-
- Absolute Address:
- Base Offset: 0x8
- Size: 0x4
-
-
-
Description
-
-
Command requested for data in mailbox
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
command
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
-
Mailbox DataOut
-
-
-
- Absolute Address:
- Base Offset: 0x14
- Size: 0x4
-
-
-
Description
-
-
Data out register, read the next data from mailbox
-
-
-
-
Contents
-
-
-
- Encoded Register Value:
-
-
-
Field Descriptions
-
-
dataout
-
-
-
-
-
- Property
- Value
-
-
- resetsignal^.^.cptra_rst_b
-
-
-
-
-
.
- * and can be redistributed under the terms of GNU GPL v3 .
- * and can be redistributed under the terms of GNU GPL v3
-
-
-
-
-
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deleted file mode 100644
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diff --git a/src/soc_ifc/docs/caliptra_top_reg_html/index.html b/src/soc_ifc/docs/caliptra_top_reg_html/index.html
deleted file mode 100644
index 5a9b5211c..000000000
--- a/src/soc_ifc/docs/caliptra_top_reg_html/index.html
+++ /dev/null
@@ -1,124 +0,0 @@
-
-
-
-
- caliptra_top_reg Reference
-
-
-
-
Keyboard Shortcuts
-
- / Open Search
- Ctrl +/ Open Search relative to current page
- Ctrl +[ and Ctrl +] Cycle through path index editors
- Ctrl +\ Navigate to parent page
-
-
-
-
-
-
\ No newline at end of file
diff --git a/src/soc_ifc/docs/caliptra_top_reg_html/js/address_search.js b/src/soc_ifc/docs/caliptra_top_reg_html/js/address_search.js
deleted file mode 100644
index eeb4d112a..000000000
--- a/src/soc_ifc/docs/caliptra_top_reg_html/js/address_search.js
+++ /dev/null
@@ -1,33 +0,0 @@
-// This file is part of PeakRDL-html .
-// and can be redistributed under the terms of GNU GPL v3 .
-// and can be redistributed under the terms of GNU GPL v3 = 2){
- for(var j=0; j {
- this.#bucket_files[bidx] = data;
- });
- return awaitable;
- }
-
-
- static async #get_matches(keywords, abortSignal){
-
- // Find locations of matching keywords
- var match_list = [];
- var match_hashtable = {};
- var itercount = 0;
- for(var i=0; i {
- return a.compare_rank_to(b);
- });
-
- return match_list;
- }
-
-
- static async #fetch_match_preview_text(match){
- return fetch_page_content(match.page_id).then(text => {
- var dp = new DOMParser();
- var doc = dp.parseFromString(text, "text/html");
-
- // Prune out the element that is most relevant to the content match
- var el;
- var el_id;
- if(match.is_field) {
- if(match.is_name) {
- // use field's row in table, since it contains the name
- el_id = match.field_name;
- } else {
- // field's description block
- el_id = "_Content." + match.field_name + ".desc";
- }
- } else {
- // Not a field
- if(match.is_name) {
- // Use page title
- el_id = "_Content.name";
- } else {
- // main description block
- el_id = "_Content.desc";
- }
- }
- var el = doc.getElementById(el_id);
-
- // strip HTML tags
- text = el.textContent;
-
- // Reduce excess whitespace
- text = text.replace(/\s+/g, " ");
-
- // Mark all keywords in content
- var keywords = Array.from(new Set([...match.full_match_keywords, ...match.partial_match_keywords]));
- var regex = new RegExp("(?:\\b|_)(" + keywords.join("|") + ")", "ig");
- var marked_text = "";
- var prev_idx = 0;
- for (const m of text.matchAll(regex)) {
- var m_idx = m.index;
-
- // advance match past underscore if it is in match
- if(text[m_idx] == "_") m_idx += 1;
-
- // Pass through prior segment
- if(prev_idx < m_idx) {
- var unmarked_segment = text.slice(prev_idx, m_idx);
- if(unmarked_segment.length > this.#PREVIEW_MAX_RUN_LENGTH) {
- // shorten the segment
- if(marked_text == ""){
- // is first
- unmarked_segment = this.#shorten_text_first(unmarked_segment);
- } else {
- // is middle
- unmarked_segment = this.#shorten_text_middle(unmarked_segment);
- }
- }
- marked_text += unmarked_segment;
- }
-
- // highlight segment
- marked_text += "" + m[1] + " ";
- prev_idx = m_idx + m[1].length;
- }
-
- if(prev_idx < text.length){
- // pass through last unmarked segment
- var unmarked_segment = text.slice(prev_idx, text.index);
- if(unmarked_segment.length > this.#PREVIEW_MAX_RUN_LENGTH) {
- // shorten the segment
- unmarked_segment = this.#shorten_text_last(unmarked_segment);
- }
- marked_text += unmarked_segment;
- }
-
- return marked_text;
- });
- }
-
- static #shorten_text_first(text){
- var L = this.#PREVIEW_MAX_RUN_LENGTH;
- return "\u22ef" + text.slice(text.length - L, text.length);
- }
-
- static #shorten_text_middle(text){
- var L = this.#PREVIEW_MAX_RUN_LENGTH;
- return text.slice(0, L/2) + "\u22ef \u22ef" + text.slice(text.length - L/2, text.length);
- }
-
- static #shorten_text_last(text){
- var L = this.#PREVIEW_MAX_RUN_LENGTH;
- return text.slice(0, L) + "\u22ef";
- }
-}
-
-
-class ContentSearchMatch {
- constructor(location_entry){
- this.full_match_keywords = new Set();
- this.partial_match_keywords = new Set();
- this.page_id = location_entry[0];
-
- var location_code = location_entry[1];
- this.is_name = Boolean(location_code & 0x1);
- this.is_enum = Boolean(location_code & 0x4);
- this.is_field = Boolean(location_code & 0x2);
- if(this.is_field){
- var field_idx = (location_code >> 3);
- this.field_name = RAL.get_node(this.page_id).fields[field_idx].name;
- } else {
- this.field_name = null;
- }
- }
-
- get_location_key(){
- // unique key that represents mergeable match location
- return String([this.page_id, this.field_name]);
- }
-
- get_matched_keywords(){
- return new Set([...this.full_match_keywords, ...this.partial_match_keywords]);
- }
-
- compare_rank_to(other){
- // +1: other has higher rank than this
- // -1: other has lower rank than this
- // 0: Other is the same rank
- var this_merged_keywords = this.get_matched_keywords();
- var other_merged_keywords = other.get_matched_keywords();
-
- // Total number of matching keywords is most important
- if(this_merged_keywords.size < other_merged_keywords.size) return 1;
- if(this_merged_keywords.size > other_merged_keywords.size) return -1;
-
- // then whichever has more full matches
- if(this.full_match_keywords.size < other.full_match_keywords.size) return 1;
- if(this.full_match_keywords.size > other.full_match_keywords.size) return -1;
-
- // then whichever has more partial matches
- if(this.partial_match_keywords.size < other.partial_match_keywords.size) return 1;
- if(this.partial_match_keywords.size > other.partial_match_keywords.size) return -1;
-
- return 0;
- }
-}
diff --git a/src/soc_ifc/docs/caliptra_top_reg_html/js/field_testers.js b/src/soc_ifc/docs/caliptra_top_reg_html/js/field_testers.js
deleted file mode 100644
index 4418cd96a..000000000
--- a/src/soc_ifc/docs/caliptra_top_reg_html/js/field_testers.js
+++ /dev/null
@@ -1,213 +0,0 @@
-// This file is part of PeakRDL-html .
-// and can be redistributed under the terms of GNU GPL v3 > lsb;
- var mask = (1n << (msb - lsb + 1n)) - 1n;
- value = value & mask;
- var el = document.getElementById("_FieldValueTester" + node.fields[idx].name);
- el.value = format_field_value(idx, value);
- el.classList.remove("invalid");
-
- if("encode" in RAL.get_node(CurrentID).fields[idx]) {
- var el = document.getElementById("_FieldValueEnumTester" + node.fields[idx].name);
- el.value = "0x" + value.toString(16);
- }
-}
-
-function format_field_value(idx, value) {
- if(RAL.get_node(CurrentID).fields[idx].disp == "D"){
- return(value.toString());
- } else {
- return("0x" + value.toString(16));
- }
-}
-
-function update_field_enum_visibility(idx){
- var node = RAL.get_node(CurrentID);
-
- if(!("encode" in node.fields[idx])) return;
-
- var d = node.fields[idx].disp;
- var enum_el = document.getElementById("_FieldValueEnumTester" + node.fields[idx].name);
- var txt_el = document.getElementById("_FieldValueTester" + node.fields[idx].name);
- if(d == "E") {
- enum_el.style.display = "inline";
- txt_el.style.display = "none";
- } else {
- enum_el.style.display = "none";
- txt_el.style.display = "inline";
- }
-}
-
-//==============================================================================
-// Events
-//==============================================================================
-
-function onRadixSwitch(el){
- var idx = RAL.lookup_field_idx(el.dataset.name);
- var node = RAL.get_node(CurrentID);
- var d = node.fields[idx].disp;
- if(d == "H") {
- d = "D";
- } else if((d == "D") && ("encode" in node.fields[idx])) {
- d = "E";
- } else {
- d = "H";
- }
-
- el.innerHTML = d;
- node.fields[idx].disp = d;
- update_field_enum_visibility(idx);
- update_field_value_tester(idx);
-}
-
-function onDecodedFieldEnumChange(el) {
- var idx = RAL.lookup_field_idx(el.dataset.name);
- var el2 = document.getElementById("_FieldValueTester" + RAL.get_node(CurrentID).fields[idx].name);
- el2.value = el.value;
- update_reg_value_tester();
- save_reg_state();
-}
-
-function onDecodedFieldInput(el){
- var idx = RAL.lookup_field_idx(el.dataset.name);
- var node = RAL.get_node(CurrentID);
- var msb = BigInt(node.fields[idx].msb);
- var lsb = BigInt(node.fields[idx].lsb);
- var value;
-
- try {
- value = BigInt(el.value);
- } catch(error) {
- value = -1n;
- }
-
- var max_value = 1n << (msb - lsb + 1n);
- if((value < 0) || (value >= max_value)){
- if(!el.classList.contains("invalid")) el.classList.add("invalid");
- return;
- }
- el.classList.remove("invalid");
-
- if("encode" in node.fields[idx]) {
- var el2 = document.getElementById("_FieldValueEnumTester" + node.fields[idx].name);
- el2.value = "0x" + value.toString(16);
- }
- update_reg_value_tester();
- save_reg_state();
-}
-
-function onEncodedRegInput(el){
- var value;
- try {
- value = BigInt(el.value);
- } catch(error) {
- value = -1n;
- }
-
- if(value < 0){
- if(!el.classList.contains("invalid")) el.classList.add("invalid");
- return;
- }
- el.classList.remove("invalid");
- update_field_value_testers();
- save_reg_state();
-}
-
-function onResetRegValue(el){
- reset_field_inputs();
- save_reg_state();
-}
diff --git a/src/soc_ifc/docs/caliptra_top_reg_html/js/index_edit.js b/src/soc_ifc/docs/caliptra_top_reg_html/js/index_edit.js
deleted file mode 100644
index e99f80921..000000000
--- a/src/soc_ifc/docs/caliptra_top_reg_html/js/index_edit.js
+++ /dev/null
@@ -1,162 +0,0 @@
-// This file is part of PeakRDL-html .
-// and can be redistributed under the terms of GNU GPL v3 .
-// and can be redistributed under the terms of GNU GPL v3 Oops! "
- + "Most modern browser's security policies "
- + "prevent this page from loading properly when using the file:// protocol.
"
- + "If possible, host this page on a web server and access using the http:// protocol.
"
-
- + "Alternatives "
- ;
-
- if(platform_is_windows()) {
- html_str +=
- "Use one of the included launcher scripts "
- + ""
- + "In the folder that contains these docs, double-click the launcher for the browser of your choice:"
- + "
"
- + " launcher-windows-chrome.batlauncher-windows-edge.batlauncher-windows-firefox.bat "
- + "These launcher scripts will temporarily disable the security setting so you can view this page locally."
- + ""
- ;
- }
-
- if(platform_is_windows()) {
- html_str +=
- "Python http server "
- + ""
- + "Launch a temporary http server using Python:"
- + "
"
- + " If you haven't already, download and install Python "
- + " "
- + " Press WIN +R and paste the following into the text box:"
- + "
"
- + " "
- + " Click 'Ok' "
- + " Re-open this page via: http://localhost:8000/ "
- + " "
- + ""
- ;
- } else {
- html_str +=
- "Python http server "
- + ""
- + "Launch a temporary http server using Python:"
- + "
"
- + 'python3 -m http.server -d "' + this_dir + '"'
- + " "
- + "Then view via: http://localhost:8000/ "
- + ""
- ;
- }
-
- html_str +=
- "Firefox "
- + ""
- + "Change your Firefox security settings:"
- + "
"
- + " In your address bar, type about:config "
- + " Set security.fileuri.strict_origin_policy to false "
- + " Refresh this page "
- + " "
- + ""
- ;
-
- if(platform_is_windows()) {
- html_str +=
- "Chrome or Edge "
- + ""
- + "
"
- + " Close your current Chrome or Edge browser session completely "
- + " "
- + " Press WIN +R and paste the following into the text box:"
- + "
"
- + " For Microsoft Edge, replace 'chrome.exe' with 'msedge.exe'"
- + " "
- + " Click 'Ok' "
- + " "
- + ""
- ;
- } else {
- html_str +=
- "Chrome "
- + ""
- + "Close your current Chrome session and re-launch it from the command-line using:"
- + "
"
- + "google-chrome --allow-file-access-from-files \\\n"
- + ' "' + window.location.href + '"'
- + " "
- + ""
- ;
- }
-
- var el = document.getElementById("_ContentContainer");
- el.innerHTML = html_str;
-}
-
-function show_incompatibility_nag() {
- var el = document.getElementById("_ContentContainer");
- el.innerHTML
- = "Nope! "
- + "It looks like the browser you are using is not supported.
"
- + "Please use a modern browser such as "
- + "Firefox "
- + " or Chrome .
"
- ;
-}
-
-function test_browser_incompatible() {
- // Test for browser features that absolutely have to exist
- try {
- var url = new URL(window.location.href);
- } catch(error) {
- return true;
- }
- return false;
-}
-
-function update_crumbtrail(){
- var crumb_el = document.getElementById("_Crumbtrail");
- var id = CurrentID;
-
- // Delete old crumbtrail
- while (crumb_el.hasChildNodes()) {
- crumb_el.removeChild(crumb_el.lastChild);
- }
-
- var path_ids = RAL.get_ids_in_path(id);
- var crumb_idx_span_idx = 0;
-
- for(var i=0; i setTimeout(r, 1));
-}
-
-function difference(setA, setB) {
- const _difference = new Set(setA);
- for (const elem of setB) {
- _difference.delete(elem);
- }
- return _difference;
-}
-
-function toBigInt(str) {
- // bigInt doesn't handle large hex strings if they use the 0x prefix
- // Wrap auto-base handling
- str = str.trim().toLowerCase();
- if(str.startsWith("0x")) {
- return(bigInt(str.substring(2), 16));
- } else if(str.startsWith("0o")) {
- return(bigInt(str.substring(2), 8));
- } else if(str.startsWith("0b")) {
- return(bigInt(str.substring(2), 2));
- } else {
- return(bigInt(str));
- }
-}
-
-function page_specific_key(key){
- var url = new URL(window.location.href);
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diff --git a/src/soc_ifc/docs/caliptra_top_reg_html/js/nav.js b/src/soc_ifc/docs/caliptra_top_reg_html/js/nav.js
deleted file mode 100644
index e6e37e96a..000000000
--- a/src/soc_ifc/docs/caliptra_top_reg_html/js/nav.js
+++ /dev/null
@@ -1,209 +0,0 @@
-// This file is part of PeakRDL-html .
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- break;
- }
- }
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-
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Error(f);this._progressPath.animate(a,b,c)},g.prototype.stop=function(){if(null===this._progressPath)throw new Error(f);void 0!==this._progressPath&&this._progressPath.stop()},g.prototype.pause=function(){if(null===this._progressPath)throw new Error(f);void 0!==this._progressPath&&this._progressPath._tweenable&&this._progressPath._tweenable.pause()},g.prototype.resume=function(){if(null===this._progressPath)throw new Error(f);void 0!==this._progressPath&&this._progressPath._tweenable&&this._progressPath._tweenable.resume()},g.prototype.destroy=function(){if(null===this._progressPath)throw new Error(f);this.stop(),this.svg.parentNode.removeChild(this.svg),this.svg=null,this.path=null,this.trail=null,this._progressPath=null,null!==this.text&&(this.text.parentNode.removeChild(this.text),this.text=null)},g.prototype.set=function(a){if(null===this._progressPath)throw new Error(f);this._progressPath.set(a)},g.prototype.value=function(){if(null===this._progressPath)throw new Error(f);return void 0===this._progressPath?0:this._progressPath.value()},g.prototype.setText=function(a){if(null===this._progressPath)throw new Error(f);null===this.text&&(this.text=this._createTextContainer(this._opts,this._container),this._container.appendChild(this.text)),e.isObject(a)?(e.removeChildren(this.text),this.text.appendChild(a)):this.text.innerHTML=a},g.prototype._createSvgView=function(a){var b=document.createElementNS("http://www.w3.org/2000/svg","svg");this._initializeSvg(b,a);var c=null;(a.trailColor||a.trailWidth)&&(c=this._createTrail(a),b.appendChild(c));var d=this._createPath(a);return b.appendChild(d),{svg:b,path:d,trail:c}},g.prototype._initializeSvg=function(a,b){a.setAttribute("viewBox","0 0 100 100")},g.prototype._createPath=function(a){var b=this._pathString(a);return this._createPathElement(b,a)},g.prototype._createTrail=function(a){var b=this._trailString(a),c=e.extend({},a);return c.trailColor||(c.trailColor="#eee"),c.trailWidth||(c.trailWidth=c.strokeWidth),c.color=c.trailColor,c.strokeWidth=c.trailWidth,c.fill=null,this._createPathElement(b,c)},g.prototype._createPathElement=function(a,b){var c=document.createElementNS("http://www.w3.org/2000/svg","path");return c.setAttribute("d",a),c.setAttribute("stroke",b.color),c.setAttribute("stroke-width",b.strokeWidth),b.fill?c.setAttribute("fill",b.fill):c.setAttribute("fill-opacity","0"),c},g.prototype._createTextContainer=function(a,b){var c=document.createElement("div");c.className=a.text.className;var d=a.text.style;return d&&(a.text.autoStyleContainer&&(b.style.position="relative"),e.setStyles(c,d),d.color||(c.style.color=a.color)),this._initializeTextContainer(a,b,c),c},g.prototype._initializeTextContainer=function(a,b,c){},g.prototype._pathString=function(a){throw new Error("Override this function for each progress bar")},g.prototype._trailString=function(a){throw new Error("Override this function for each progress bar")},g.prototype._warnContainerAspectRatio=function(a){if(this.containerAspectRatio){var b=window.getComputedStyle(a,null),c=parseFloat(b.getPropertyValue("width"),10),d=parseFloat(b.getPropertyValue("height"),10);e.floatEquals(this.containerAspectRatio,c/d)||(console.warn("Incorrect aspect ratio of container","#"+a.id,"detected:",b.getPropertyValue("width")+"(width)","/",b.getPropertyValue("height")+"(height)","=",c/d),console.warn("Aspect ratio of should be",this.containerAspectRatio))}},b.exports=g},{"./path":5,"./utils":9}],8:[function(a,b,c){var d=a("./shape"),e=a("./utils"),f=function(a,b){this._pathTemplate="M 0,{halfOfStrokeWidth} L {width},{halfOfStrokeWidth} L {width},{width} L {halfOfStrokeWidth},{width} L {halfOfStrokeWidth},{strokeWidth}",this._trailTemplate="M {startMargin},{halfOfStrokeWidth} L {width},{halfOfStrokeWidth} L {width},{width} L {halfOfStrokeWidth},{width} L {halfOfStrokeWidth},{halfOfStrokeWidth}",d.apply(this,arguments)};f.prototype=new d,f.prototype.constructor=f,f.prototype._pathString=function(a){var b=100-a.strokeWidth/2;return e.render(this._pathTemplate,{width:b,strokeWidth:a.strokeWidth,halfOfStrokeWidth:a.strokeWidth/2})},f.prototype._trailString=function(a){var b=100-a.strokeWidth/2;return e.render(this._trailTemplate,{width:b,strokeWidth:a.strokeWidth,halfOfStrokeWidth:a.strokeWidth/2,startMargin:a.strokeWidth/2-a.trailWidth/2})},b.exports=f},{"./shape":7,"./utils":9}],9:[function(a,b,c){function d(a,b,c){a=a||{},b=b||{},c=c||!1;for(var e in b)if(b.hasOwnProperty(e)){var f=a[e],g=b[e];c&&l(f)&&l(g)?a[e]=d(f,g,c):a[e]=g}return a}function e(a,b){var c=a;for(var d in b)if(b.hasOwnProperty(d)){var e=b[d],f="\\{"+d+"\\}",g=new RegExp(f,"g");c=c.replace(g,e)}return c}function f(a,b,c){for(var d=a.style,e=0;e.
-// and can be redistributed under the terms of GNU GPL v3 {
- this.#increment_progressbar();
- this.#ral_data_files[idx] = data;
- })
- .catch(e => {
- this.#destroy_progressbar();
- throw new Error("fetch failed");
- });
- return awaitable;
- }
-
- static #progress_points = 0;
- static #progressbar = null;
- static #init_progressbar(){
- this.#progressbar = new ProgressBar.Circle("#_ProgressBar", {
- strokeWidth: 10, // forces extra padding
- trailWidth: 3,
- text: {
- value: "Loading..."
- }
- });
-
- if(N_RAL_FILES == 1){
- // Only one object to load. animate progress as stand-in.
- this.#progressbar.animate(1, {duration:400});
- }
- }
- static #increment_progressbar(){
- this.#progress_points++;
- this.#progressbar.set(this.#progress_points / N_RAL_FILES);
- if(this.#progress_points == N_RAL_FILES) {
- this.#destroy_progressbar();
- }
- }
-
- static #destroy_progressbar(){
- this.#progressbar.destroy();
- this.#progressbar = null;
- }
-
- static get_node(id){
- var file_idx = Math.floor(id / N_RAL_NODES_PER_FILE);
- var idx = id % N_RAL_NODES_PER_FILE;
- var node = this.#ral_data_files[file_idx][idx];
- this.#expand_bigint(node);
- return node;
- }
-
- static #expand_bigint(node){
- // Check if RAL entry has been converted yet
- if(typeof node.offset !== 'string') return;
-
- // Needs conversion from base-16 string --> BigInt object
- node.offset = BigInt("0x" + node.offset);
- node.size = BigInt("0x" + node.size);
- if('stride' in node) node.stride = BigInt("0x" + node.stride);
-
- if(RAL.is_register_node(node)) {
- for(var i=0; i= segment_idxs[0].length){
- sanitized_idxs.push(0);
- } else {
- sanitized_idxs.push(Math.min(segment_idxs[0][dim], this.get_node(id).dims[dim]-1));
- }
- }
- segment_idxs[0] = sanitized_idxs;
- } else {
- if(segment_idxs[0].length != 0) segment_idxs[0] = [];
- }
-
- // Validate the path and find the end ID
- for(var i=1; i= segment_idxs[i].length){
- sanitized_idxs.push(0);
- } else {
- sanitized_idxs.push(Math.min(segment_idxs[i][dim], this.get_node(id).dims[dim]-1));
- }
- }
- segment_idxs[i] = sanitized_idxs;
- } else {
- if(segment_idxs[i].length != 0) segment_idxs[i] = [];
- }
- }
-
- return([id, segment_idxs]);
- }
-
- static apply_idx_stack(id, idx_stack){
- // Applies the given index stack onto the RAL
- // Assumes the indexes are valid
- for(var i=idx_stack.length-1; i>=0; i--){
- if(idx_stack[i].length){
- this.get_node(id).idxs = idx_stack[i];
- }
- id = this.get_node(id).parent;
- }
- }
-
- static get_path(id, idx_stack, show_idx){
- if(typeof idx_stack === "undefined") idx_stack = null;
- if(typeof show_idx === "undefined") show_idx = true;
-
- // Get string representation of the hierarchical path
- if(show_idx && (idx_stack == null)){
- idx_stack = this.get_current_idx_stack(id);
- }
- var ids = this.get_ids_in_path(id);
- var pathparts = [];
- for(var i=0; i= (this.get_node(id).offset + this.get_total_size(id))) return(null);
-
- while(iter_count < 100){
- iter_count++;
- // addr is definitely inside this node
-
- // Adjust addr to be relative to this node
- addr = addr - this.get_node(id).offset;
-
- // Determine index stack entry for this node
- if(this.is_array(id)){
- var idxs = [];
-
- // First check if address lands between sparse array entries
- if((addr % this.get_node(id).stride) >= this.get_node(id).size) {
- // missed! Give up and just return the parent node
- if(this.get_node(id).parent == null){
- return(null);
- }else{
- return([this.get_node(id).parent, idx_stack]);
- }
- }
-
- // index of the flattened array
- var flat_idx = Number(addr / this.get_node(id).stride);
-
- // Re-construct dimensions
- for(var dim=this.get_node(id).dims.length-1; dim>=0; dim--){
- var idx;
- idx = flat_idx % this.get_node(id).dims[dim];
- flat_idx = Math.floor(flat_idx / this.get_node(id).dims[dim]);
- idxs.unshift(idx);
- }
- idx_stack.push(idxs);
-
- // Adjust addr offset to be relative to this index
- addr = addr % this.get_node(id).stride;
- } else {
- idx_stack.push([]);
- }
-
- // Search this node's children to see which child 'addr' is in
- var found_match = false;
- for(var i=0; i= this.get_node(child).offset) && (addr < (this.get_node(child).offset + this.get_total_size(child)))){
- // hit!
- id = child;
- found_match = true;
- break;
- }
- }
- if(!found_match){
- // No further match. Current node is the result
- return([id, idx_stack]);
- }
- }
-
- // Hit iteration limit. Something is wrong :-(
- throw "Agh! iteration limit reached while looking up by address";
- }
-
- static lookup_field_idx(name) {
- var node = this.get_node(CurrentID);
- for(var i=0; i.
-// and can be redistributed under the terms of GNU GPL v3 tag.
- // text_segments[0] --> not highlighted
- // text_segments[1] --> highlighted
-
- var result_idx = SearchState.results.length;
- var result_el = document.createElement("li");
- result_el.onclick = function() {
- open_search_result(result_idx);
- };
- result_el.onmousemove = function() {
- onSearchResultMousemove(result_idx)
- };
- var path_div_el = document.createElement("div");
- result_el.appendChild(path_div_el);
-
- // Build highlighted path crumbtrail
- for(var i=0; i {
- Sidebar.expand_to_id(result.node_id);
- Sidebar.select_node(result.node_id);
- Sidebar.scroll_into_view(result.node_id);
- refresh_url(url_hash);
- refresh_title();
- refresh_target_scroll();
- });
-}
diff --git a/src/soc_ifc/docs/caliptra_top_reg_html/js/sha1.js b/src/soc_ifc/docs/caliptra_top_reg_html/js/sha1.js
deleted file mode 100644
index 8dd714108..000000000
--- a/src/soc_ifc/docs/caliptra_top_reg_html/js/sha1.js
+++ /dev/null
@@ -1,173 +0,0 @@
-/**
-*
-* Secure Hash Algorithm (SHA1)
-* http://www.webtoolkit.info/
-*
-**/
-
-function SHA1(msg) {
-
- function rotate_left(n,s) {
- var t4 = ( n<>>(32-s));
- return t4;
- };
-
- function lsb_hex(val) {
- var str="";
- var i;
- var vh;
- var vl;
-
- for( i=0; i<=6; i+=2 ) {
- vh = (val>>>(i*4+4))&0x0f;
- vl = (val>>>(i*4))&0x0f;
- str += vh.toString(16) + vl.toString(16);
- }
- return str;
- };
-
- function cvt_hex(val) {
- var str="";
- var i;
- var v;
-
- for( i=7; i>=0; i-- ) {
- v = (val>>>(i*4))&0x0f;
- str += v.toString(16);
- }
- return str;
- };
-
-
- function Utf8Encode(string) {
- string = string.replace(/\r\n/g,"\n");
- var utftext = "";
-
- for (var n = 0; n < string.length; n++) {
-
- var c = string.charCodeAt(n);
-
- if (c < 128) {
- utftext += String.fromCharCode(c);
- }
- else if((c > 127) && (c < 2048)) {
- utftext += String.fromCharCode((c >> 6) | 192);
- utftext += String.fromCharCode((c & 63) | 128);
- }
- else {
- utftext += String.fromCharCode((c >> 12) | 224);
- utftext += String.fromCharCode(((c >> 6) & 63) | 128);
- utftext += String.fromCharCode((c & 63) | 128);
- }
-
- }
-
- return utftext;
- };
-
- var blockstart;
- var i, j;
- var W = new Array(80);
- var H0 = 0x67452301;
- var H1 = 0xEFCDAB89;
- var H2 = 0x98BADCFE;
- var H3 = 0x10325476;
- var H4 = 0xC3D2E1F0;
- var A, B, C, D, E;
- var temp;
-
- msg = Utf8Encode(msg);
-
- var msg_len = msg.length;
-
- var word_array = new Array();
- for( i=0; i>>29 );
- word_array.push( (msg_len<<3)&0x0ffffffff );
-
-
- for ( blockstart=0; blockstart.
-// and can be redistributed under the terms of GNU GPL v3 =0; i--){
- var current_id = id_chain[i];
- var el = this.#get_node_el(current_id);
- if(el == null){
- // doesnt exist. it will get expanded once created
- node_ids_to_expand.unshift(current_id);
- } else {
- // reached node that exists already
- if(el.classList.contains("closed")){
- // .. but it is still closed
- node_ids_to_expand.unshift(current_id);
- }
- break;
- }
- }
-
- // Create missing elements
- for(var i=0; i 0){
- if(el.classList.contains("open")){
- return; // already open
- }
-
- var cdiv;
- cdiv = document.createElement("div");
- cdiv.className = "node-children";
- el.after(cdiv);
-
- for(var i=0; i 0){
- if(el.classList.contains("closed")){
- return; // already closed
- }
- var cdiv = el.nextElementSibling;
- if(cdiv.classList.contains('node-children')){
- cdiv.remove();
- } else {
- console.error("OOPS");
- }
- el.classList.add("closed")
- el.classList.remove("open")
- }
- }
-
- static collapse_all(){
- for(var i=0; i 0){
- // has children
- div.classList.add("closed");
-
- var cdiv;
- cdiv = document.createElement("div");
- cdiv.className = "node-children";
- parent_el.appendChild(cdiv);
- } else {
- // is leaf node
- div.classList.add("leaf");
- }
- }
-
- static select_node(id) {
- // Changes the selected tree node
- var el;
- if(this.#selected_node_id != null){
- el = this.#get_node_el(this.#selected_node_id)
- if(el != null){ // element might have already been deleted
- el.classList.remove("selected");
- }
- }
-
- el = this.#get_node_el(id);
- el.classList.add("selected");
- this.#selected_node_id = id;
- }
-
- static #onResizeMouseDown(e) {
- var sb_el = document.getElementById("_SBContents");
- this.#resizer_old_width = sb_el.getBoundingClientRect().width;
- this.#resizer_start_x = e.clientX;
- window.addEventListener('mousemove', this.#mousemove_cb);
- window.addEventListener('mouseup', this.#mouseup_cb);
- e.preventDefault();
- }
-
- static #onResizeMouseMove(e) {
- var sb_el = document.getElementById("_SBContents");
- var new_width;
- new_width = this.#resizer_old_width + e.clientX - this.#resizer_start_x;
- sb_el.style.width = new_width + "px";
- }
-
- static #onResizeMouseUp(e) {
- window.removeEventListener('mousemove', this.#mousemove_cb);
- window.removeEventListener('mouseup', this.#mouseup_cb);
-
- // remember sidebar width
- var sb_el = document.getElementById("_SBContents");
- localStorage.setItem(page_specific_key("sb_width"), sb_el.style.width);
- }
-
- static show() {
- document.getElementById("_Sidebar").style.display = "flex";
- document.getElementById("_Overlay").style.display = "block";
- }
-
- static hide() {
- document.getElementById("_Sidebar").style.display = "none";
- document.getElementById("_Overlay").style.display = "none";
- }
-
- static scroll_into_view(id){
- var node_el = this.#get_node_el(id);
- var tree_el = document.getElementById("_SBTreeContainer");
-
- var node_rect = node_el.getBoundingClientRect();
- var tree_rect = tree_el.getBoundingClientRect();
-
- if(
- (node_rect.top < tree_rect.top)
- || (node_rect.bottom > tree_rect.bottom)
- || (node_rect.left < tree_rect.left)
- || (node_rect.right > tree_rect.right)
- ) {
- node_el.scrollIntoView({
- block: "nearest",
- inline: "start"
- });
- }
- }
-}
-
-function onClickTreeFold(ev) {
- var el = ev.target.parentNode;
- var id = parseInt(el.dataset.id);
- if(el.classList.contains("leaf")) return;
-
- if(el.classList.contains("closed")){
- // Open this node
- Sidebar.expand_node(id);
-
- // may need to re-select current
- Sidebar.select_node(CurrentID);
- }else{
- // Close this node
- Sidebar.collapse_node(id);
- }
-}
-
-function onClickTreeLink(ev) {
- var el = ev.target.parentNode;
- var id = parseInt(el.dataset.id);
-
- close_search();
- Sidebar.hide();
-
- if(id == CurrentID) return(false);
-
- if(!el.classList.contains("leaf")){
- Sidebar.expand_node(id);
- }
-
- RAL.reset_indexes_to_next(id);
-
- load_page(id).then(() => {
- Sidebar.expand_to_id(id);
- Sidebar.select_node(id);
- refresh_url();
- refresh_title();
- refresh_target_scroll();
- });
- return(false);
-}
-
-function onClickTreeExpandAll() {
- Sidebar.expand_all()
-
- // may need to re-select current
- Sidebar.select_node(CurrentID);
-}
-
-function onClickTreeCollapseAll() {
- Sidebar.collapse_all()
-}
diff --git a/src/soc_ifc/docs/caliptra_top_reg_html/launcher-windows-chrome.bat b/src/soc_ifc/docs/caliptra_top_reg_html/launcher-windows-chrome.bat
deleted file mode 100644
index 09bd64c89..000000000
--- a/src/soc_ifc/docs/caliptra_top_reg_html/launcher-windows-chrome.bat
+++ /dev/null
@@ -1,17 +0,0 @@
-@echo off&setlocal
-
-:: set some convenience variables
-for %%i in ("%~dp0.") do set "this_dir=%%~fi"
-set "docpath=file://%this_dir%\index.html"
-set "launcher_data=%this_dir%\.launcher_data"
-
-:: Launch using Chrome using some special flags:
-:: --allow-file-access-from-files
-:: This flag works around a security policy that prevents dynamic content to be loaded
-:: See this page for more details:
-:: https://developer.mozilla.org/en-US/docs/Web/HTTP/CORS/Errors/CORSRequestNotHttp
-:: --user-data-dir
-:: If chrome already has a session open, then it will re-use that session and the CORS workaround
-:: will not take effect. Forcing chrome to use a temporary alternate user data directory
-:: is a hacky way to force chrome to launch a fresh session
-start "" chrome --allow-file-access-from-files --user-data-dir=%launcher_data%\chrome %docpath%
diff --git a/src/soc_ifc/docs/caliptra_top_reg_html/launcher-windows-edge.bat b/src/soc_ifc/docs/caliptra_top_reg_html/launcher-windows-edge.bat
deleted file mode 100644
index 36cb2a62e..000000000
--- a/src/soc_ifc/docs/caliptra_top_reg_html/launcher-windows-edge.bat
+++ /dev/null
@@ -1,19 +0,0 @@
-@echo off&setlocal
-
-:: set some convenience variables
-for %%i in ("%~dp0.") do set "this_dir=%%~fi"
-set "docpath=file://%this_dir%\index.html"
-set "launcher_data=%this_dir%\.launcher_data"
-
-:: Launch using Edge using some special flags:
-:: --allow-file-access-from-files
-:: This flag works around a security policy that prevents dynamic content to be loaded
-:: See this page for more details:
-:: https://developer.mozilla.org/en-US/docs/Web/HTTP/CORS/Errors/CORSRequestNotHttp
-:: --user-data-dir
-:: If edge already has a session open, then it will re-use that session and the CORS workaround
-:: will not take effect. Forcing edge to use a temporary alternate user data directory
-:: is a hacky way to force edge to launch a fresh session
-:: NOTE: Edge may prompt you with a few "new user" popups the first time, because
-:: the data dir is uninitialized. I could not figure out a clean way to disable this
-start "" msedge --allow-file-access-from-files --user-data-dir=%launcher_data%\msedge %docpath%
diff --git a/src/soc_ifc/docs/caliptra_top_reg_html/launcher-windows-firefox.bat b/src/soc_ifc/docs/caliptra_top_reg_html/launcher-windows-firefox.bat
deleted file mode 100644
index 132f22322..000000000
--- a/src/soc_ifc/docs/caliptra_top_reg_html/launcher-windows-firefox.bat
+++ /dev/null
@@ -1,14 +0,0 @@
-@echo off&setlocal
-
-:: set some convenience variables
-for %%i in ("%~dp0.") do set "this_dir=%%~fi"
-set "docpath=file://%this_dir%\index.html"
-set "launcher_data=%this_dir%\.launcher_data"
-
-:: Launch using Firefox using a pre-configured profile
-:: This profile sets the user preference:
-:: security.fileuri.strict_origin_policy = false
-:: This setting works around a security policy that prevents dynamic content to be loaded
-:: See this page for more details:
-:: https://developer.mozilla.org/en-US/docs/Web/HTTP/CORS/Errors/CORSRequestNotHttp
-start "" firefox -profile %launcher_data%\firefox %docpath%
diff --git a/src/soc_ifc/docs/caliptra_top_reg_html/search/bkt-0.json b/src/soc_ifc/docs/caliptra_top_reg_html/search/bkt-0.json
deleted file mode 100644
index d5851dff6..000000000
--- a/src/soc_ifc/docs/caliptra_top_reg_html/search/bkt-0.json
+++ /dev/null
@@ -1 +0,0 @@
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\ No newline at end of file
diff --git a/src/soc_ifc/docs/caliptra_top_reg_html/search/bkt_index.js b/src/soc_ifc/docs/caliptra_top_reg_html/search/bkt_index.js
deleted file mode 100644
index 175c35453..000000000
--- a/src/soc_ifc/docs/caliptra_top_reg_html/search/bkt_index.js
+++ /dev/null
@@ -1 +0,0 @@
-var SearchBucketIndex = [267651219];
\ No newline at end of file