[entropy_src] Keep applying fw_ov_rd_fifo_overflow (#506)

Keep applying fw_ov_rd_fifo_overflow instead of pulsing. This commit is
a manual port of the following Opentitan commit:

b454878f2528b49318ff2b604cb8d59a6e59b0ea

Which is associated with
lowRISC/opentitan#21640.

Original commit description:

This commit applies the fw_ov_rd_fifo_overflow signal in case of an
overflow. It used to only send a pulse through the register but now
the signal is applied until the FIFO has been emptied once and is
receiving contiguous data again.
This commit also aligns the documentation for the FW_OV_RD_FIFO_OVERFLOW
register. The register is now not clearable by software. It instead
is cleared by hardware.

Signed-off-by: Miguel Osorio <[email protected]>

.github/workflow_metadata/pr_hash

@@ -1 +1 @@
-6d4ab4825024ab9ac6bdd9da7f697e8c46e778b62f31e18c38ef227f4a39095cea032f79f1686a79f5d49c1b5604f1c4
+6cd6271af5cc73b4c69623c0fb3354d0d211b459c36b1c0820075afadd8ce3eda9f3f4c0e50ae2f8b96f2e74b837f94b

.github/workflow_metadata/pr_timestamp

@@ -1 +1 @@
-1713994941
+1714005956

src/entropy_src/data/entropy_src.hjson

@@ -1176,7 +1176,7 @@
     },
     { name:     "FW_OV_RD_FIFO_OVERFLOW",
       desc:     "Firmware override Observe FIFO overflow status",
-      swaccess: "rw0c",
+      swaccess: "ro",
       hwaccess: "hwo",
       hwext: "false",
       fields: [
@@ -1187,7 +1187,7 @@
                 in the Observe FIFO. The RNG data rate is slow enough that firmware should always
                 be able to keep up. This register meanwhile provides an additional check to confirm
                 that bytes read from the !!FW_OV_RD_DATA register represent contiguous RNG samples.
-                If an overflow event occurs, this bit must be cleared by software.
+                If an overflow event occurs, this bit is cleared by hardware as soon as the FIFO is emptied.
                 '''
         }
       ]

src/entropy_src/data/entropy_src.json

@@ -1072,14 +1072,14 @@
     {
       "name": "FW_OV_RD_FIFO_OVERFLOW",
       "desc": "Firmware override Observe FIFO overflow status",
-      "swaccess": "rw0c",
+      "swaccess": "ro",
       "hwaccess": "hwo",
       "hwext": "false",
       "fields": [
         {
           "bits": "0",
           "name": "FW_OV_RD_FIFO_OVERFLOW",
-          "desc": "This bit is set by hardware whenever RNG data is lost due to an overflow condition\nin the Observe FIFO. The RNG data rate is slow enough that firmware should always\nbe able to keep up. This register meanwhile provides an additional check to confirm\nthat bytes read from the !!FW_OV_RD_DATA register represent contiguous RNG samples.\nIf an overflow event occurs, this bit must be cleared by software."
+          "desc": "This bit is set by hardware whenever RNG data is lost due to an overflow condition\nin the Observe FIFO. The RNG data rate is slow enough that firmware should always\nbe able to keep up. This register meanwhile provides an additional check to confirm\nthat bytes read from the !!FW_OV_RD_DATA register represent contiguous RNG samples.\nIf an overflow event occurs, this bit is cleared by hardware as soon as the FIFO is emptied."
         }
       ]
     },
@@ -1366,4 +1366,4 @@
       ]
     }
   ]
-}
+}

src/entropy_src/data/entropy_src.rdl

@@ -688,9 +688,8 @@ addrmap entropy_src {
             in the Observe FIFO. The RNG data rate is slow enough that firmware should always
             be able to keep up. This register meanwhile provides an additional check to confirm
             that bytes read from the !!FW_OV_RD_DATA register represent contiguous RNG samples.
-            If an overflow event occurs, this bit must be cleared by software.";
-            sw = rw;
-            onwrite = woclr;
+            If an overflow event occurs, this bit is cleared by hardware as soon as the FIFO is emptied.";
+            sw = r;
         } FW_OV_RD_FIFO_OVERFLOW[0:0];
     } FW_OV_RD_FIFO_OVERFLOW @ 0xBC;
     reg {

src/entropy_src/rtl/entropy_src_core.sv

@@ -5,8 +5,8 @@
 // Description: entropy_src core module
 //
 
-module entropy_src_core 
-  import entropy_src_pkg::*; 
+module entropy_src_core
+  import entropy_src_pkg::*;
   import lc_ctrl_state_pkg::*;
   import lc_ctrl_reg_pkg::*;
   import lc_ctrl_pkg::*;
@@ -2336,8 +2336,8 @@ module entropy_src_core
   // contiguous as possible.
   logic sfifo_observe_gate_d, sfifo_observe_gate_q;
 
-  assign sfifo_observe_gate_d = (sfifo_observe_push && sfifo_observe_full) ? 1'b0 :
-                                !sfifo_observe_not_empty                   ? 1'b1 :
+  assign sfifo_observe_gate_d = (pfifo_postht_pop && sfifo_observe_full) ? 1'b0 :
+                                !sfifo_observe_not_empty                 ? 1'b1 :
                                 sfifo_observe_gate_q;
 
   always_ff @(posedge clk_i or negedge rst_ni) begin
@@ -2348,7 +2348,7 @@ module entropy_src_core
     end
   end
 
-  assign hw2reg.fw_ov_rd_fifo_overflow.d  = (pfifo_postht_pop && sfifo_observe_full);
+  assign hw2reg.fw_ov_rd_fifo_overflow.d  = !sfifo_observe_gate_d;
   assign hw2reg.fw_ov_rd_fifo_overflow.de = 1'b1;
 
   assign observe_fifo_thresh_met = fw_ov_mode && (observe_fifo_thresh != '0) &&

src/entropy_src/rtl/entropy_src_reg_top.sv

@@ -2222,15 +2222,15 @@ module entropy_src_reg_top #(
   // R[fw_ov_rd_fifo_overflow]: V(False)
   caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_fw_ov_rd_fifo_overflow (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
-    .we     (fw_ov_rd_fifo_overflow_we),
-    .wd     (fw_ov_rd_fifo_overflow_wd),
+    .we     (1'b0),
+    .wd     ('0),
 
     // from internal hardware
     .de     (hw2reg.fw_ov_rd_fifo_overflow.de),
@@ -3476,9 +3476,7 @@ module entropy_src_reg_top #(
 
   assign fw_ov_sha3_start_wd = reg_wdata[3:0];
   assign fw_ov_wr_fifo_full_re = addr_hit[46] & reg_re & !reg_error;
-  assign fw_ov_rd_fifo_overflow_we = addr_hit[47] & reg_we & !reg_error;
 
-  assign fw_ov_rd_fifo_overflow_wd = reg_wdata[0];
   assign fw_ov_rd_data_re = addr_hit[48] & reg_re & !reg_error;
   assign fw_ov_wr_data_we = addr_hit[49] & reg_we & !reg_error;
 
@@ -3573,7 +3571,7 @@ module entropy_src_reg_top #(
     reg_we_check[44] = fw_ov_control_gated_we;
     reg_we_check[45] = fw_ov_sha3_start_we;
     reg_we_check[46] = 1'b0;
-    reg_we_check[47] = fw_ov_rd_fifo_overflow_we;
+    reg_we_check[47] = 1'b0;
     reg_we_check[48] = 1'b0;
     reg_we_check[49] = fw_ov_wr_data_we;
     reg_we_check[50] = observe_fifo_thresh_gated_we;