Extend CI matrix #56

Job	Run time
generate-config	4s
build-spike / Build Spike	6s
generate-code (riscv_arithmetic_basic_test)	1m 25s
generate-code (riscv_rand_instr_test)	1m 20s
generate-code (riscv_jump_stress_test)	1m 16s
generate-code (riscv_loop_test)	1m 18s
generate-code (riscv_rand_jump_test)	1m 20s
generate-code (riscv_mmu_stress_test)	1m 22s
generate-code (riscv_no_fence_test)	1m 20s
generate-code (riscv_illegal_instr_test)	1m 25s
generate-code (riscv_ebreak_test)	1m 15s
generate-code (riscv_ebreak_debug_mode_test)	1m 29s
generate-code (riscv_full_interrupt_test)	1m 28s
generate-code (riscv_unaligned_load_store_test)	1m 18s
generate-code (riscv_non_compressed_instr_test)	1m 19s
generate-code (riscv_hint_instr_test)	1m 23s
generate-code (riscv_pmp_test)	1m 24s
test-riscv (riscv_arithmetic_basic_test, uvm)	1m 10s
test-riscv (riscv_rand_instr_test, uvm)	55s
test-riscv (riscv_jump_stress_test, uvm)	1m 4s
test-riscv (riscv_loop_test, uvm)	1m 9s
test-riscv (riscv_rand_jump_test, uvm)	58s
test-riscv (riscv_mmu_stress_test, uvm)	1m 2s
test-riscv (riscv_no_fence_test, uvm)	58s
test-riscv (riscv_illegal_instr_test, uvm)	59s
test-riscv (riscv_ebreak_test, uvm)	1m 5s
test-riscv (riscv_ebreak_debug_mode_test, uvm)	1m 25s
test-riscv (riscv_full_interrupt_test, uvm)	1m 2s
test-riscv (riscv_unaligned_load_store_test, uvm)	52s
test-riscv (riscv_non_compressed_instr_test, uvm)	1m 18s
test-riscv (riscv_hint_instr_test, uvm)	1m 6s
test-riscv (riscv_pmp_test, uvm)	1m 3s
test-riscv (riscv_arithmetic_basic_test, pyflow)	2m 46s
	39m 24s

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