Fixed some compilation issues

chipsalliance · Feb 27, 2024 · 4a68deb · 4a68deb
1 parent a7a56c7
commit 4a68deb
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Showing 2 changed files with 7 additions and 7 deletions.
diff --git a/euvm/riscv/gen/riscv_page_table_entry.d b/euvm/riscv/gen/riscv_page_table_entry.d
@@ -161,13 +161,13 @@ class riscv_page_table_entry(satp_mode_t MODE = satp_mode_t.SV39) : uvm_object
   void pack_entry() {
     switch (MODE) {
     case satp_mode_t.SV32:
-      bits = ppn1 ~ ppn0 ~ rsw ~ d ~ a ~ g ~ u ~ toubvec!3(xwr) ~ v;
+      bits = ppn1 ~ ppn0 ~ rsw ~ d ~ a ~ g ~ u ~ xwr ~ v;
       break;
     case satp_mode_t.SV39:
-      bits = cast(ubvec!XLEN) (rsvd ~ ppn2 ~ ppn1 ~ ppn0 ~ rsw ~ d ~ a ~ g ~ u ~ toubvec!3(xwr) ~ v);
+      bits = cast(ubvec!XLEN) (rsvd ~ ppn2 ~ ppn1 ~ ppn0 ~ rsw ~ d ~ a ~ g ~ u ~ xwr ~ v);
       break;
     case satp_mode_t.SV48:
-      bits = cast(ubvec!XLEN) (rsvd ~ ppn3 ~ ppn2 ~ ppn1 ~ ppn0 ~ rsw ~ d ~ a ~ g ~ u ~ toubvec!3(xwr) ~ v);
+      bits = cast(ubvec!XLEN) (rsvd ~ ppn3 ~ ppn2 ~ ppn1 ~ ppn0 ~ rsw ~ d ~ a ~ g ~ u ~ xwr ~ v);
       break;
     default:
       uvm_fatal(get_full_name(), format("Unsupported mode %0x", MODE));

diff --git a/euvm/riscv/gen/riscv_privileged_common_seq.d b/euvm/riscv/gen/riscv_privileged_common_seq.d
@@ -127,15 +127,15 @@ class riscv_privileged_common_seq: uvm_sequence!(uvm_sequence_item,uvm_sequence_
     mstatus.set_field("FS", cfg.mstatus_fs);
     mstatus.set_field("VS", cfg.mstatus_vs);
     if (!(canFind(supported_privileged_mode, privileged_mode_t.SUPERVISOR_MODE)) && (XLEN != 32)) {
-      mstatus.set_field("SXL", toubvec!2(0b00));
+      mstatus.set_field("SXL", UBVEC!(2, 0b00));
     }
     else if (XLEN == 64) {
-      mstatus.set_field("SXL", toubvec!2(0b10));
+      mstatus.set_field("SXL", UBVEC!(2, 0b10));
     }
     if (!(canFind(supported_privileged_mode, privileged_mode_t.USER_MODE)) && (XLEN != 32)) {
-      mstatus.set_field("UXL", toubvec!2(0b00));
+      mstatus.set_field("UXL", UBVEC!(2, 0b00));
     } else if (XLEN == 64) {
-      mstatus.set_field("UXL", toubvec!2(0b10));
+      mstatus.set_field("UXL", UBVEC!(2, 0b10));
     }
     mstatus.set_field("XS", 0);
     mstatus.set_field("SD", 0);