Added parallelism to euvm port

.github/scripts/parse_testlist.py

@@ -0,0 +1,26 @@
+import sys
+from json import dumps
+from yaml import load, Loader
+from typing import Generator
+
+
+def parse_yaml(path: str) -> Generator[str, None, None]:
+    with open(path, 'rb') as fd:
+        tests = load(fd, Loader=Loader)
+    for test in tests:
+        if 'import' in test:
+            import_path = test['import'].split('/', 1)[1]
+            yield from parse_yaml(import_path)
+        elif 'test' in test:
+            yield test['test']
+
+
+if __name__ == "__main__":
+    if len(sys.argv) == 2:
+        testlist = parse_yaml(f'target/{sys.argv[1]}/testlist.yaml')
+    else:
+        testlist = parse_yaml('yaml/base_testlist.yaml')
+    testlist = list(testlist)
+    # remove, will cause incomplete sim, need customized RTL
+    testlist.remove("riscv_csr_test")
+    print(dumps(testlist))

.github/workflows/run-tests.yml

@@ -4,22 +4,119 @@ on:
   push:
   pull_request:
 
+env:
+  RISCV_TARGET: rv32imc
+
 jobs:
   build-spike:
     uses: ./.github/workflows/build-spike.yml
-  test-pyflow:
+
+  generate-config:
+    runs-on: ubuntu-latest
+    outputs:
+      test-types: ${{ steps.test-types.outputs.tests }}
+      hash: ${{ steps.hash.outputs.files-hash }}
+    steps:
+      - uses: actions/checkout@v4
+      - id: test-types
+        name: Prepare test types
+        run: |
+          python3 -m pip install pyyaml
+          echo "tests=$(python3 .github/scripts/parse_testlist.py $RISCV_TARGET)" | tee -a $GITHUB_OUTPUT
+      - id: hash
+        name: Prepare files' hash
+        run: |
+          echo "files-hash=$(sha256sum **/*.sv **/*.py **/*.yml **/*.yaml | cut -d\  -f1 | sha256sum | cut -d\  -f1)" | tee -a $GITHUB_OUTPUT
+
+
+  generate-code:
+    runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]
+    container: centos:8
+    needs: generate-config
     strategy:
       fail-fast: false
       matrix:
-        test:
-          - riscv_arithmetic_basic_test
+        test: ${{ fromJSON(needs.generate-config.outputs.test-types) }}
+        version: [ uvm ]
+        include:
+          - test: riscv_arithmetic_basic_test 
+            version: pyflow
+    env:
+      GHA_EXTERNAL_DISK: additional-tools
+      CACHE_HASH: ${{ needs.generate-config.outputs.hash }}
+    steps:
+      - uses: actions/checkout@v3
+
+      - name: Setup Cache Metadata
+        id: cache_metadata
+        run: |
+          cache_code=cache_${{ matrix.test }}_${{ matrix.version }}
+          echo "cache_code=${cache_code}_${{ env.CACHE_HASH }}" | tee -a "$GITHUB_ENV"
+
+      - name: Cache Code
+        uses: actions/cache@v3
+        id: cache-code
+        timeout-minutes: 60
+        with:
+          path: test/asm_test
+          key: ${{ env.cache_code }}
+
+      - name: Prepare Environment
+        if: steps.cache-code.outputs.cache-hit != 'true'
+        run: _secret_environment
+
+      - name: Setup Python 3.9
+        if: steps.cache-code.outputs.cache-hit != 'true'
+        run: |
+          yum update -y
+          yum install -y python39
+          python3.9 -m pip install -r requirements.txt
+
+      - name: Generate UVM Tests
+        if: steps.cache-code.outputs.cache-hit != 'true' && matrix.version == 'uvm'
+        run: _secret_riscv
+        env:
+          RISCV_TEST: ${{ matrix.test }}
+          RISCV_TARGET: ${{ env.RISCV_TARGET }}
+
+      - name: Generate PyFlow Tests
+        if: steps.cache-code.outputs.cache-hit != 'true' && matrix.version == 'pyflow'
+        run: |
+          set -eo pipefail
+          python3 run.py --simulator pyflow \
+            --test ${{ matrix.test }} --iss spike \
+            --start_seed 999 --iterations 1 --batch_size 1 \
+            --isa $RISCV_TARGET --mabi ilp32 --steps gen -v -o test 2>&1 | tee test/generate.log
+
+      - name: Upload Artifacts
+        uses: actions/upload-artifact@v3
+        if: always()
+        with:
+          path: |
+            test/asm_test/*.S
+
+
+  run-tests:
     runs-on: ubuntu-latest
-    needs: [build-spike]
+    needs: [ build-spike, generate-code, generate-config ]
+    strategy:
+      fail-fast: false
+      matrix:
+        test: ${{ fromJSON(needs.generate-config.outputs.test-types) }}
+        version:
+          - uvm
+        include:
+          - test: riscv_arithmetic_basic_test
+            version: pyflow
+    env:
+      TOOL_VERSION: d70ea67d
+      CACHE_HASH: ${{ needs.generate-config.outputs.hash }}
+
     steps:
       - uses: actions/checkout@v4
 
       - name: Install dependencies
-        run: sudo apt-get -qqy update && sudo apt-get -qqy install gcc-riscv64-linux-gnu device-tree-compiler
+        run: sudo apt-get -qqy update && sudo apt-get -qqy install gcc-riscv64-unknown-elf device-tree-compiler
 
       - name: Setup python
         # python dependencies cannot be properly downloaded with new versions of python
@@ -36,10 +133,12 @@ jobs:
           date=$(date +"%Y_%m_%d")
           time=$(date +"%Y%m%d_%H%M%S_%N")
           cache_spike_restore_key=cache_spike_
-          cache_spike_key=${cache_spike_restore_key}d70ea67d_${date}
+          cache_spike_key=${cache_spike_restore_key}${{ env.TOOL_VERSION }}_${date}
+          cache_code=cache_${{ matrix.test }}_${{ matrix.version }}
 
           echo "cache_spike_restore_key=$cache_spike_restore_key" | tee -a "$GITHUB_ENV"
           echo "cache_spike_key=$cache_spike_key" | tee -a "$GITHUB_ENV"
+          echo "cache_code=${cache_code}_${{ env.CACHE_HASH }}" | tee -a "$GITHUB_ENV"
 
       - name: Restore Spike cache
         id: cache-spike-restore
@@ -53,31 +152,28 @@ jobs:
 
       - name: Set variables
         run: |
-          echo "RISCV_GCC=riscv64-linux-gnu-gcc" >> $GITHUB_ENV
-          echo "RISCV_OBJCOPY=riscv64-linux-gnu-objcopy" >> $GITHUB_ENV
+          echo "RISCV_GCC=riscv64-unknown-elf-gcc" >> $GITHUB_ENV
+          echo "RISCV_OBJCOPY=riscv64-unknown-elf-objcopy" >> $GITHUB_ENV
           echo "SPIKE_PATH=/opt/spike/bin" >> $GITHUB_ENV
           echo "PYTHONPATH=pygen" >> $GITHUB_ENV
 
-      - name: Generate Tests
-        run: |
-          set -eo pipefail
-          python3 run.py --simulator pyflow \
-            --test ${{ matrix.test }} --iss spike \
-            --start_seed 999 --iterations 1 --batch_size 1 \
-            --isa rv32imc --mabi ilp32 --steps gen -v -o test 2>&1 | tee test/generate.log
-
-      - name: Patch Tests
-        run: find test/asm_test -name "*.S" -exec python3 .github/scripts/code_fixup.py -i {} -o {} \;
+      - name: Cache Code Restore
+        uses: actions/cache/restore@v3
+        id: cache-code-restore
+        timeout-minutes: 60
+        with:
+          path: test/asm_test
+          key: ${{ env.cache_code }}
 
-      - name: Run tests
+      - name: Run Tests
         run: |
           set -eo pipefail
           python3 run.py --simulator pyflow \
             --test ${{ matrix.test }} --iss spike --iss_timeout 60 \
             --start_seed 999 --iterations 1 --batch_size 1 \
-            --isa rv32imc --mabi ilp32 --steps gcc_compile,iss_sim -v -o test 2>&1 | tee -a test/generate.log
+            --isa $RISCV_TARGET --mabi ilp32 --steps gcc_compile,iss_sim -v -o test 2>&1 | tee -a test/generate.log
 
-      - name: Upload logs
+      - name: Upload Artifacts
         uses: actions/upload-artifact@v3
         if: always()
         with:

euvm/README.md

@@ -10,6 +10,8 @@ The RISCV-DV eUVM port is a line-by-line translation of the RISCV-DV SystemVeril
 
 If you want to build/use the eUVM port, you need an eUVM installation. Please follow the instructions on https://github.com/coverify/euvm/releases to install and setup eUVM.
 
+Please use euvm 1.0-beta36 or later release for compiling and running RISCV-DV.
+
 ## Building eUVM port of RISCV-DV
 
 A makefile to build and run the eUVM port is available in the euvm/build folder. To build the code, use the following commands (assuming bash shell):
@@ -41,3 +43,15 @@ You can change the number of instructions to be generated by passsing INSTRCOUNT
 ```bash
 make run INSTRCOUNT=1000000
 ```
+
+To run arithmatic_only_test for 10 million instructions:
+
+```
+make run_riscv_arithmetic_only_test INSTRCOUNT=10000000
+```
+
+To run arithmatic_only_test for 10 million instructions using 32 threads:
+
+```
+make run_riscv_arithmetic_only_test INSTRCOUNT=10000000 THREADS=32
+```

euvm/build/makefile

@@ -1,15 +1,19 @@
 # Runtime Paramters
+GCOPTS = # --DRT-gcopt=parallel:0
 INSTRCOUNT = 100000
 VERBOSITY = NONE
+VERSION = NOVERSION
 RANDSEED = 1
+THREADS = 1
+CPU = 4
 
 # Compile Paramters
 MTRIPLE = -m64
 TARGET = RV64IMC
 CC = gcc
 DEBUG = NONE
-DFLAGS = $(MTRIPLE) -d-version=$(TARGET) -w -d-debug=$(DEBUG) -O3  -release -boundscheck=off # --lowmem # -d-version=CHECK_COMPILE
-DBGDFLAGS = $(MTRIPLE) -d-version=$(TARGET) -w -d-debug=$(DEBUG) -g
+DFLAGS = $(MTRIPLE) -d-version=$(TARGET) -d-version=$(VERSION) -w -d-debug=$(DEBUG) -O3 -mcpu=native -release -boundscheck=off # -defaultlib=phobos2-ldc-lto,druntime-ldc-lto # --lowmem # -d-version=CHECK_COMPILE
+DBGDFLAGS = $(MTRIPLE) -d-version=$(TARGET) -w -mcpu=native -d-debug=$(DEBUG) -g
 LDC2 = ldc2
 PICOBJDIR = picobj-ldc
 DBGPICOBJDIR = picobj-dbg-ldc
@@ -20,14 +24,18 @@ PICDBGOBJDIR = picobj-dbg-ldc
 DBGOBJDIR = obj-dbg-ldc
 
 PHOBOS = phobos2-ldc-shared
+PHOBOSDBG = phobos2-ldc-debug-shared
+
 
 DATE = $(shell date '+%Y-%m-%d')
 
 GEN_FILES = riscv/gen/package.d riscv/gen/riscv_amo_instr_lib.d		\
 	    riscv/gen/riscv_data_page_gen.d				\
 	    riscv/gen/riscv_directed_instr_lib.d			\
 	    riscv/gen/riscv_instr_gen_config.d				\
+	    riscv/gen/riscv_opcodes_pkg.d				\
 	    riscv/gen/riscv_instr_pkg.d					\
+	    riscv/gen/riscv_opcodes_pkg.d				\
 	    riscv/gen/riscv_instr_registry.d				\
 	    riscv/gen/riscv_instr_sequence.d				\
 	    riscv/gen/riscv_instr_stream.d				\
@@ -53,18 +61,21 @@ GEN_FILES = riscv/gen/package.d riscv/gen/riscv_amo_instr_lib.d		\
 	    riscv/gen/target/rv64gc/riscv_core_setting.d		\
 	    riscv/gen/target/rv64imcb/riscv_core_setting.d		\
 	    riscv/gen/target/rv32imafdc/riscv_core_setting.d		\
+	    riscv/gen/target/rv64imafdc/riscv_core_setting.d		\
 	    riscv/gen/target/ml/riscv_core_setting.d			\
 	    riscv/gen/target/multi_harts/riscv_core_setting.d		\
 	    riscv/gen/target/rv32imc_sv32/riscv_core_setting.d		\
 	    riscv/gen/target/rv32i/riscv_core_setting.d			\
 	    riscv/gen/target/rv64imc/riscv_core_setting.d		\
+	    riscv/gen/target/rv64imp/riscv_core_setting.d		\
 	    riscv/gen/target/rv32imc/riscv_core_setting.d
 
 
 ISA_FILES = riscv/gen/isa/package.d riscv/gen/isa/riscv_amo_instr.d	\
             riscv/gen/isa/riscv_compressed_instr.d			\
             riscv/gen/isa/riscv_floating_point_instr.d			\
             riscv/gen/isa/riscv_instr.d riscv/gen/isa/riscv_b_instr.d	\
+            riscv/gen/isa/riscv_csr_instr.d			        \
             riscv/gen/isa/riscv_vector_instr.d				\
             riscv/gen/isa/riscv_instr_register.d			\
             riscv/gen/isa/riscv_zba_instr.d				\
@@ -87,7 +98,10 @@ ISA_FILES = riscv/gen/isa/package.d riscv/gen/isa/riscv_amo_instr.d	\
             riscv/gen/isa/rv32zbs_instr.d				\
             riscv/gen/isa/rv64zba_instr.d				\
             riscv/gen/isa/rv64zbb_instr.d				\
-            riscv/gen/isa/custom/riscv_custom_instr.d			\
+	    riscv/gen/isa/rvzpn_instr.d					\
+	    riscv/gen/isa/rv32zpn_instr.d				\
+	    riscv/gen/isa/rv64zpn_instr.d				\
+	    riscv/gen/isa/custom/riscv_custom_instr.d			\
             riscv/gen/isa/custom/riscv_custom_instr_enum.d
 
 TEST_FILES = riscv/test/riscv_instr_base_test.d                         \
@@ -118,17 +132,17 @@ $(DBGPICOBJDIR)/%.o: ../%.d
 libriscv-dv-ldc-shared.so: $(addprefix $(PICOBJDIR)/,$(GEN_OBJS)) \
 			   $(addprefix $(PICOBJDIR)/,$(ISA_OBJS)) \
 			   $(addprefix $(PICOBJDIR)/,$(TEST_OBJS))
-	CC=$(CC) $(LDC2) -shared $(DFLAGS) -relocation-model=pic -of$@ -I.. $^ -L-luvm-ldc-shared -L-lesdl-ldc-shared -L-lphobos2-ldc-shared -L-ldruntime-ldc-shared -L-lz3
+	CC=$(CC) $(LDC2) -shared $(DFLAGS) -relocation-model=pic -of$@ -I.. $^ -L-luvm-ldc-shared -L-lesdl-ldc-shared -L-lphobos2-ldc-shared -L-ldruntime-ldc-shared -L-lz3 # -L-lboolector
 
 libriscv-dv-ldc-debug-shared.so: $(addprefix $(DBGPICOBJDIR)/,$(GEN_OBJS)) \
 			         $(addprefix $(DBGPICOBJDIR)/,$(ISA_OBJS)) \
 			         $(addprefix $(DBGPICOBJDIR)/,$(TEST_OBJS))
-	CC=$(CC) $(LDC2) -shared $(DBGDFLAGS) -relocation-model=pic -of$@ -I.. $^ -L-luvm-ldc-shared -L-lesdl-ldc-shared -L-lphobos2-ldc-shared -L-ldruntime-ldc-shared -L-lz3
+	CC=$(CC) $(LDC2) -shared $(DBGDFLAGS) -relocation-model=pic -of$@ -I.. $^ -L-luvm-ldc-debug-shared -L-lesdl-ldc-debug-shared -L-lphobos2-ldc-debug-shared -L-ldruntime-ldc-debug-shared -L-lz3 # -L-lboolector
 
 libriscv-dv-ldc-shared-alt.so: $(addprefix ../,$(GEN_FILES)) \
 			       $(addprefix ../,$(ISA_FILES)) \
 			       $(addprefix $(PICOBJDIR)/,$(TEST_OBJS))
-	CC=$(CC) $(LDC2) -shared $(DFLAGS) -relocation-model=pic -of$@ -I.. $^ -L-luvm-ldc-shared -L-lesdl-ldc-shared -L-lphobos2-ldc-shared -L-ldruntime-ldc-shared -L-lz3
+	CC=$(CC) $(LDC2) -shared $(DFLAGS) -relocation-model=pic -of$@ -I.. $^ -L-luvm-ldc-shared -L-lesdl-ldc-shared -L-lphobos2-ldc-shared -L-ldruntime-ldc-shared -L-lz3  # -L-lboolector
 
 libriscv-dv-ldc.a: $(addprefix $(PICOBJDIR)/,$(GEN_OBJS)) \
 	           $(addprefix $(PICOBJDIR)/,$(ISA_OBJS)) \
@@ -141,13 +155,13 @@ TAGS: $(addprefix ../,$(GEN_FILES)) \
 	dscanner --etags $^ > $@
 
 riscv_instr_gen: ../riscv/test/riscv_instr_gen.d libriscv-dv-ldc-shared.so
-	$(LDC2) -link-defaultlib-shared $(DFLAGS) -of$@ -I.. -L--no-as-needed -L-R./ -L-L./ $< -L-lriscv-dv-ldc-shared -L-luvm-ldc-shared -L-lesdl-ldc-shared -L-lphobos2-ldc-shared -L-lz3 -L-ldl 
+	$(LDC2) -link-defaultlib-shared $(DFLAGS) -of$@ -I.. -L--no-as-needed -L-R./ -L-L./ $< -L-lriscv-dv-ldc-shared -L-luvm-ldc-shared -L-lesdl-ldc-shared -L-lz3 -L-ldl  # -L-lboolector # -defaultlib=phobos2-ldc-lto,druntime-ldc-lto
 
 riscv_instr_gen_debug: ../riscv/test/riscv_instr_gen.d libriscv-dv-ldc-debug-shared.so
-	$(LDC2) -link-defaultlib-shared $(DBGDFLAGS) -of$@ -I.. -L--no-as-needed -L-R./ -L-L./ $< -L-lriscv-dv-ldc-debug-shared -L-luvm-ldc-debug-shared -L-lesdl-ldc-debug-shared -L-lphobos2-ldc-shared -L-lz3 -L-ldl
+	$(LDC2) -link-defaultlib-shared $(DBGDFLAGS) -of$@ -I.. -L--no-as-needed -L-R./ -L-L./ $< -L-lriscv-dv-ldc-debug-shared -L-luvm-ldc-debug-shared -L-lesdl-ldc-debug-shared -L-lphobos2-ldc-debug-shared -L-ldruntime-ldc-debug-shared -L-lz3 -L-ldl  # -L-lboolector
 
 run: riscv_instr_gen
-	./riscv_instr_gen +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_$(DATE)/asm_test/riscv_rand_instr_test +instr_cnt=$(INSTRCOUNT) +num_of_sub_program=5 \
+	./riscv_instr_gen $(GCOPTS) +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +par_num_threads=$(THREADS) +thread_index=$(CPU) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_$(DATE)/asm_test/riscv_rand_instr_test +instr_cnt=$(INSTRCOUNT) +num_of_sub_program=5 \
 	+directed_instr_0=riscv.gen.riscv_load_store_instr_lib.riscv_load_store_rand_instr_stream,4 \
 	+directed_instr_1=riscv.gen.riscv_load_store_instr_lib.riscv_hazard_instr_stream,4 \
 	+directed_instr_2=riscv.gen.riscv_load_store_instr_lib.riscv_load_store_hazard_instr_stream,4 \
@@ -157,7 +171,7 @@ run: riscv_instr_gen
 	+directed_instr_6=riscv.gen.riscv_loop_instr.riscv_loop_instr,4
 
 run_debug: riscv_instr_gen_debug
-	./riscv_instr_gen_debug +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_2021-08-10/asm_test/riscv_rand_instr_test +instr_cnt=$(INSTRCOUNT) +num_of_sub_program=5 \
+	./riscv_instr_gen_debug $(GCOPTS) +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +par_num_threads=$(THREADS) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_2021-08-10/asm_test/riscv_rand_instr_test +instr_cnt=$(INSTRCOUNT) +num_of_sub_program=5 \
 	+directed_instr_0=riscv.gen.riscv_load_store_instr_lib.riscv_load_store_rand_instr_stream,4 \
 	+directed_instr_1=riscv.gen.riscv_load_store_instr_lib.riscv_hazard_instr_stream,4 \
 	+directed_instr_2=riscv.gen.riscv_load_store_instr_lib.riscv_load_store_hazard_instr_stream,4 \
@@ -167,7 +181,22 @@ run_debug: riscv_instr_gen_debug
 	+directed_instr_6=riscv.gen.riscv_loop_instr.riscv_loop_instr,4
 
 run_riscv_arithmetic_basic_test: riscv_instr_gen
-	./riscv_instr_gen +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_2021-08-10/asm_test/riscv_arithmetic_basic_test +instr_cnt=$(INSTRCOUNT) +num_of_sub_program=0 +directed_instr_0=riscv.gen.riscv_directed_instr_lib.riscv_int_numeric_corner_stream,4 +no_fence=true +no_data_page=true +no_branch_jump=true +boot_mode=m +no_csr_instr=true 
+	./riscv_instr_gen $(GCOPTS) +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +par_num_threads=$(THREADS) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_2021-08-10/asm_test/riscv_arithmetic_basic_test +instr_cnt=$(INSTRCOUNT) +num_of_sub_program=0 +directed_instr_0=riscv.gen.riscv_directed_instr_lib.riscv_int_numeric_corner_stream,4 +no_fence=true +no_data_page=true +no_branch_jump=true +boot_mode=m +no_csr_instr=true 
 
 run_riscv_arithmetic_only_test: riscv_instr_gen
-	./riscv_instr_gen +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_2021-08-10/asm_test/riscv_arithmetic_basic_test +instr_cnt=$(INSTRCOUNT) +no_fence=true +no_data_page=true +num_of_sub_program=0 +no_branch_jump=true +boot_mode=m +no_csr_instr=true 
+	./riscv_instr_gen $(GCOPTS) +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +par_num_threads=$(THREADS) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_2021-08-10/asm_test/riscv_arithmetic_basic_test +instr_cnt=$(INSTRCOUNT) +no_fence=true +no_data_page=true +num_of_sub_program=0 +no_branch_jump=true +boot_mode=m +no_csr_instr=true 
+
+run_pmp_test: riscv_instr_gen
+	./riscv_instr_gen $(GCOPTS) +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +par_num_threads=$(THREADS) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_$(DATE)/asm_test/riscv_rand_instr_test +instr_cnt=$(INSTRCOUNT) +num_of_sub_program=5 \
+	+directed_instr_0=riscv.gen.riscv_load_store_instr_lib.riscv_load_store_rand_instr_stream,4 \
+	+directed_instr_1=riscv.gen.riscv_load_store_instr_lib.riscv_hazard_instr_stream,4 \
+	+directed_instr_2=riscv.gen.riscv_load_store_instr_lib.riscv_load_store_hazard_instr_stream,4 \
+	+directed_instr_3=riscv.gen.riscv_load_store_instr_lib.riscv_multi_page_load_store_instr_stream,4 \
+	+directed_instr_4=riscv.gen.riscv_load_store_instr_lib.riscv_mem_region_stress_test,4 \
+	+directed_instr_5=riscv.gen.riscv_directed_instr_lib.riscv_jal_instr,4 \
+	+directed_instr_6=riscv.gen.riscv_loop_instr.riscv_loop_instr,4 \
+	+pmp_randomize=false \
+	+pmp_num_regions=1 \
+        +pmp_granularity=1 \
+        +pmp_region_0=L:false,A:TOR,X:true,W:true,R:true,ADDR:FFFFFFFF
+