Merge pull request #3532 from cyyself/remove_b_zk

chipsalliance · Nov 17, 2023 · 6b67317 · 6b67317
2 parents 89f46b3 + 218ae0a
commit 6b67317
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Showing 18 changed files with 269 additions and 1,950 deletions.
diff --git a/.github/workflows/mill-ci.yml b/.github/workflows/mill-ci.yml
@@ -72,7 +72,7 @@ jobs:
     if: ${{ false }}  # disable for now, I prefer adding firesim-based simulation framework in the future.
     strategy:
       matrix:
-        config: ["DefaultRV32Config,32,RV32IMACZicsr_Zifencei", "DefaultConfig,64,RV64IMACZicsr_Zifencei", "BitManipCryptoConfig,64,RV64IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh", "BitManipCrypto32Config,32,RV32IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh"]
+        config: ["DefaultRV32Config,32,RV32IMACZicsr_Zifencei", "DefaultConfig,64,RV64IMACZicsr_Zifencei"]
     steps:
       - uses: actions/checkout@v2
         with:

diff --git a/build.sc b/build.sc
@@ -203,7 +203,7 @@ trait Emulator extends Cross.Module2[String, String] {
         "debug_rob.cc",
         "emulator.cc",
         "remote_bitbang.cc",
-      ).map(c => PathRef(csrcDir().path / c))
+        ).map(c => PathRef(csrcDir().path / c))
     }
 
     def CMakeListsString = T {
@@ -313,8 +313,6 @@ object emulator extends Cross[Emulator](
   //
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config"),
-  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCryptoConfig"),
-  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCrypto32Config"),
 )
 
 object `runnable-riscv-test` extends mill.Cross[RiscvTest](
@@ -402,9 +400,6 @@ object `runnable-arch-test` extends mill.Cross[ArchTest](
   // For CI within reasonable time
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultConfig", "64", "RV64IMACZicsr_Zifencei"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config", "32", "RV32IMACZicsr_Zifencei"),
-
-  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCryptoConfig", "64", "RV64IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh"),
-  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCrypto32Config", "32", "RV32IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh"),
 )
 
 object `runnable-jtag-dtm-test` extends mill.Cross[JTAGDTMTest](

diff --git a/scripts/arch-test/emulator/riscof_emulator.py b/scripts/arch-test/emulator/riscof_emulator.py
@@ -111,30 +111,6 @@ def build(self, isa_yaml, platform_yaml):
           self.isa += '_Zicsr'
       if "Zifencei" in ispec["ISA"]:
           self.isa += '_Zifencei'
-      if "Zba" in ispec["ISA"]:
-          self.isa += '_Zba'
-      if "Zbb" in ispec["ISA"]:
-          self.isa += '_Zbb'
-      if "Zbc" in ispec["ISA"]:
-          self.isa += '_Zbc'
-      if "Zbkb" in ispec["ISA"]:
-          self.isa += '_Zbkb'
-      if "Zbkc" in ispec["ISA"]:
-          self.isa += '_Zbkc'
-      if "Zbkx" in ispec["ISA"]:
-          self.isa += '_Zbkx'
-      if "Zbs" in ispec["ISA"]:
-          self.isa += '_Zbs'
-      if "Zknd" in ispec["ISA"]:
-          self.isa += '_Zknd'
-      if "Zkne" in ispec["ISA"]:
-          self.isa += '_Zkne'
-      if "Zknh" in ispec["ISA"]:
-          self.isa += '_Zknh'
-      if "Zksed" in ispec["ISA"]:
-          self.isa += '_Zksed'
-      if "Zksh" in ispec["ISA"]:
-          self.isa += '_Zksh'
 
       #TODO: The following assumes you are using the riscv-gcc toolchain. If
       #      not please change appropriately

diff --git a/scripts/arch-test/spike/riscof_spike.py b/scripts/arch-test/spike/riscof_spike.py
@@ -111,30 +111,6 @@ def build(self, isa_yaml, platform_yaml):
           self.isa += '_Zicsr'
       if "Zifencei" in ispec["ISA"]:
           self.isa += '_Zifencei'
-      if "Zba" in ispec["ISA"]:
-          self.isa += '_Zba'
-      if "Zbb" in ispec["ISA"]:
-          self.isa += '_Zbb'
-      if "Zbc" in ispec["ISA"]:
-          self.isa += '_Zbc'
-      if "Zbkb" in ispec["ISA"]:
-          self.isa += '_Zbkb'
-      if "Zbkc" in ispec["ISA"]:
-          self.isa += '_Zbkc'
-      if "Zbkx" in ispec["ISA"]:
-          self.isa += '_Zbkx'
-      if "Zbs" in ispec["ISA"]:
-          self.isa += '_Zbs'
-      if "Zknd" in ispec["ISA"]:
-          self.isa += '_Zknd'
-      if "Zkne" in ispec["ISA"]:
-          self.isa += '_Zkne'
-      if "Zknh" in ispec["ISA"]:
-          self.isa += '_Zknh'
-      if "Zksed" in ispec["ISA"]:
-          self.isa += '_Zksed'
-      if "Zksh" in ispec["ISA"]:
-          self.isa += '_Zksh'
 
       #TODO: The following assumes you are using the riscv-gcc toolchain. If
       #      not please change appropriately