Fix VHDL and SystemVerilog gen for Xilinx oddr
#3441
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| name: Kloonbot | |
| on: issue_comment | |
| jobs: | |
| kloonbot: | |
| name: Clone branch to local branch | |
| runs-on: ubuntu-latest | |
| if: ${{ github.event.issue.pull_request }} | |
| env: | |
| KBOT_AUTHOR_ASSOC: ${{ github.event.comment.author_association }} | |
| KBOT_COMMENT: ${{ github.event.comment.body }} | |
| KBOT_PULL_REQUEST_URL: ${{ github.event.issue.pull_request.url }} | |
| steps: | |
| - name: Checkout | |
| uses: actions/checkout@v2 | |
| - run: | | |
| ./.ci/kloonbot.sh |