First active edge at least one clock period from start

Fixes #2001
clash-lang · Nov 21, 2021 · 06c0bfb · 06c0bfb
1 parent 88ced73
commit 06c0bfb
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Showing 27 changed files with 134 additions and 102 deletions.
diff --git a/Clash.hs b/Clash.hs
@@ -35,34 +35,34 @@ import Util (OverridingBool(..))
 genSystemVerilog
   :: String
   -> IO ()
-genSystemVerilog = doHDL (initBackend WORD_SIZE_IN_BITS HDLSYN True PreserveCase Nothing (AggressiveXOptBB False) (RenderEnums True) :: SystemVerilogState)
+genSystemVerilog = doHDL (initBackend WORD_SIZE_IN_BITS HDLSYN True PreserveCase Nothing (AggressiveXOptBB False) (RenderEnums True) :: DomainMap -> SystemVerilogState)
 
 genVHDL
   :: String
   -> IO ()
-genVHDL = doHDL (initBackend WORD_SIZE_IN_BITS HDLSYN True PreserveCase Nothing (AggressiveXOptBB False) (RenderEnums True) :: VHDLState)
+genVHDL = doHDL (initBackend WORD_SIZE_IN_BITS HDLSYN True PreserveCase Nothing (AggressiveXOptBB False) (RenderEnums True) :: DomainMap -> VHDLState)
 
 genVerilog
   :: String
   -> IO ()
-genVerilog = doHDL (initBackend WORD_SIZE_IN_BITS HDLSYN True PreserveCase Nothing (AggressiveXOptBB False) (RenderEnums True) :: VerilogState)
+genVerilog = doHDL (initBackend WORD_SIZE_IN_BITS HDLSYN True PreserveCase Nothing (AggressiveXOptBB False) (RenderEnums True) :: DomainMap -> VerilogState)
 
 doHDL
   :: HasCallStack
   => Backend s
-  => s
+  => (DomainMap -> s)
   -> String
   -> IO ()
 doHDL b src = do
   startTime <- Clock.getCurrentTime
-  pd      <- primDirs b
+  pd      <- primDirs (b emptyDomainMap)
   (bindingsMap,tcm,tupTcm,topEntities,primMap,reprs,domainConfs) <-
-    generateBindings (return ()) Auto pd ["."] [] (hdlKind b) src Nothing
+    generateBindings (return ()) Auto pd ["."] [] (hdlKind (b emptyDomainMap)) src Nothing
   prepTime <- startTime `deepseq` bindingsMap `deepseq` tcm `deepseq` reprs `deepseq` Clock.getCurrentTime
   let prepStartDiff = reportTimeDiff prepTime startTime
   putStrLn $ "Loading dependencies took " ++ prepStartDiff
 
-  generateHDL (buildCustomReprs reprs) domainConfs bindingsMap (Just b) primMap tcm tupTcm
+  generateHDL (buildCustomReprs reprs) domainConfs bindingsMap (Just (b domainConfs)) primMap tcm tupTcm
     (ghcTypeToHWType WORD_SIZE_IN_BITS True) ghcEvaluator evaluator topEntities Nothing
     defClashOpts{opt_cachehdl = False, opt_debug = debugSilent, opt_clear = True}
     (startTime,prepTime)

diff --git a/benchmark/common/BenchmarkCommon.hs b/benchmark/common/BenchmarkCommon.hs
@@ -63,7 +63,7 @@ hdl :: HDL
 hdl = VHDL
 
 backend :: VHDLState
-backend = initBackend WORD_SIZE_IN_BITS HDLSYN True PreserveCase Nothing (AggressiveXOptBB False) (RenderEnums True)
+backend = initBackend WORD_SIZE_IN_BITS HDLSYN True PreserveCase Nothing (AggressiveXOptBB False) (RenderEnums True) emptyDomainMap
 
 runInputStage
   :: [FilePath]

diff --git a/changelog/2021-11-19T17_41_41+01_00_fix2001 b/changelog/2021-11-19T17_41_41+01_00_fix2001
@@ -0,0 +1 @@
+FIXED: Clash now generates clock generators that ensure that the amount of time between simulation start and the first active edge of the clock is equal to (/or longer than/) the period of the clock. The first active edges of the clocks do still occur simultaneously. [#2001](https://github.com/clash-lang/clash-compiler/issues/2001)
diff --git a/clash-ghc/src-bin-8.10/Clash/GHCi/UI.hs b/clash-ghc/src-bin-8.10/Clash/GHCi/UI.hs
@@ -146,7 +146,7 @@ import Clash.GHCi.Leak
 
 -- clash additions
 import qualified Clash.Backend
-import           Clash.Backend (AggressiveXOptBB, RenderEnums)
+import           Clash.Backend (AggressiveXOptBB, DomainMap, RenderEnums, emptyDomainMap)
 import           Clash.Backend.SystemVerilog (SystemVerilogState)
 import           Clash.Backend.VHDL (VHDLState)
 import           Clash.Backend.Verilog (VerilogState)
@@ -2143,7 +2143,7 @@ exceptT :: Applicative m => Either e a -> ExceptT e m a
 exceptT = ExceptT . pure
 
 makeHDL' :: Clash.Backend.Backend backend
-         => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> backend)
+         => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> backend)
          -> IORef ClashOpts
          -> [FilePath]
          -> InputT GHCi ()
@@ -2184,7 +2184,7 @@ makeHDL' backend opts lst = go =<< case lst of
 
 makeHDL :: GHC.GhcMonad m
         => Clash.Backend.Backend backend
-        => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> backend)
+        => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> backend)
         -> GHC.Ghc ()
         -> IORef ClashOpts
         -> [FilePath]
@@ -2203,7 +2203,7 @@ makeHDL backend startAction optsRef srcs = do
                   frcUdf = opt_forceUndefined opts1
                   xOptBB = opt_aggressiveXOptBB opts1
                   enums  = opt_renderEnums opts1
-                  hdl    = Clash.Backend.hdlKind backend'
+                  hdl    = Clash.Backend.hdlKind backendE
                   -- determine whether `-outputdir` was used
                   outputDir = do odir <- objectDir dflags
                                  hidir <- hiDir dflags
@@ -2216,11 +2216,12 @@ makeHDL backend startAction optsRef srcs = do
                   opts2 = opts1 { opt_hdlDir = maybe outputDir Just (opt_hdlDir opts1)
                                 , opt_importPaths = idirs}
                   backend' = backend iw syn esc lw frcUdf (coerce xOptBB) (coerce enums)
+                  backendE = backend' emptyDomainMap
 
               checkMonoLocalBinds dflags
               checkImportDirs opts0 idirs
 
-              primDirs <- Clash.Backend.primDirs backend'
+              primDirs <- Clash.Backend.primDirs backendE
 
               forM_ srcs $ \src -> do
                 -- Generate bindings:
@@ -2239,7 +2240,7 @@ makeHDL backend startAction optsRef srcs = do
                   (buildCustomReprs reprs)
                   domainConfs
                   bindingsMap
-                  (Just backend')
+                  (Just (backend' domainConfs))
                   primMap
                   tcm
                   tupTcm

diff --git a/clash-ghc/src-bin-8.10/Clash/Main.hs b/clash-ghc/src-bin-8.10/Clash/Main.hs
@@ -91,7 +91,7 @@ import           Data.IORef (IORef, newIORef, readIORef)
 import qualified Data.Version (showVersion)
 
 import qualified Clash.Backend
-import           Clash.Backend (AggressiveXOptBB, RenderEnums)
+import           Clash.Backend (AggressiveXOptBB, RenderEnums, DomainMap)
 import           Clash.Backend.SystemVerilog (SystemVerilogState)
 import           Clash.Backend.VHDL    (VHDLState)
 import           Clash.Backend.Verilog (VerilogState)
@@ -1005,7 +1005,7 @@ abiHash strs = do
 
 makeHDL'
   :: Clash.Backend.Backend backend
-  => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> backend)
+  => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> backend)
   -> Ghc () -> IORef ClashOpts -> [(String,Maybe Phase)] -> Ghc ()
 makeHDL' _       _           _ []   = throwGhcException (CmdLineError "No input files")
 makeHDL' backend startAction r srcs = makeHDL backend startAction r $ fmap fst srcs

diff --git a/clash-ghc/src-bin-861/Clash/GHCi/UI.hs b/clash-ghc/src-bin-861/Clash/GHCi/UI.hs
@@ -140,7 +140,7 @@ import Clash.GHCi.Leak
 
 -- clash additions
 import qualified Clash.Backend
-import           Clash.Backend (AggressiveXOptBB, RenderEnums)
+import           Clash.Backend (AggressiveXOptBB, DomainMap, RenderEnums, emptyDomainMap)
 import           Clash.Backend.SystemVerilog (SystemVerilogState)
 import           Clash.Backend.VHDL (VHDLState)
 import           Clash.Backend.Verilog (VerilogState)
@@ -1974,7 +1974,7 @@ exceptT :: Applicative m => Either e a -> ExceptT e m a
 exceptT = ExceptT . pure
 
 makeHDL' :: Clash.Backend.Backend backend
-         => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> backend)
+         => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> backend)
          -> IORef ClashOpts
          -> [FilePath]
          -> InputT GHCi ()
@@ -2015,7 +2015,7 @@ makeHDL' backend opts lst = go =<< case lst of
 
 makeHDL :: GHC.GhcMonad m
         => Clash.Backend.Backend backend
-        => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> backend)
+        => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> backend)
         -> GHC.Ghc ()
         -> IORef ClashOpts
         -> [FilePath]
@@ -2034,7 +2034,7 @@ makeHDL backend startAction optsRef srcs = do
                   frcUdf = opt_forceUndefined opts1
                   xOptBB = opt_aggressiveXOptBB opts1
                   enums  = opt_renderEnums opts1
-                  hdl    = Clash.Backend.hdlKind backend'
+                  hdl    = Clash.Backend.hdlKind backendE
                   -- determine whether `-outputdir` was used
                   outputDir = do odir <- objectDir dflags
                                  hidir <- hiDir dflags
@@ -2047,11 +2047,12 @@ makeHDL backend startAction optsRef srcs = do
                   opts2 = opts1 { opt_hdlDir = maybe outputDir Just (opt_hdlDir opts1)
                                 , opt_importPaths = idirs}
                   backend' = backend iw syn esc lw frcUdf (coerce xOptBB) (coerce enums)
+                  backendE = backend' emptyDomainMap
 
               checkMonoLocalBinds dflags
               checkImportDirs opts0 idirs
 
-              primDirs <- Clash.Backend.primDirs backend'
+              primDirs <- Clash.Backend.primDirs backendE
 
               forM_ srcs $ \src -> do
                 -- Generate bindings:
@@ -2069,7 +2070,7 @@ makeHDL backend startAction optsRef srcs = do
                   (buildCustomReprs reprs)
                   domainConfs
                   bindingsMap
-                  (Just backend')
+                  (Just (backend' domainConfs))
                   primMap
                   tcm
                   tupTcm
@@ -2082,13 +2083,13 @@ makeHDL backend startAction optsRef srcs = do
                   (startTime,prepTime)
 
 makeVHDL :: IORef ClashOpts -> [FilePath] -> InputT GHCi ()
-makeVHDL = makeHDL' (Clash.Backend.initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> VHDLState)
+makeVHDL = makeHDL' (Clash.Backend.initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> VHDLState)
 
 makeVerilog :: IORef ClashOpts -> [FilePath] -> InputT GHCi ()
-makeVerilog = makeHDL' (Clash.Backend.initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> VerilogState)
+makeVerilog = makeHDL' (Clash.Backend.initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> VerilogState)
 
 makeSystemVerilog :: IORef ClashOpts -> [FilePath] -> InputT GHCi ()
-makeSystemVerilog = makeHDL' (Clash.Backend.initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> SystemVerilogState)
+makeSystemVerilog = makeHDL' (Clash.Backend.initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> SystemVerilogState)
 
 -----------------------------------------------------------------------------
 -- | @:type@ command. See also Note [TcRnExprMode] in TcRnDriver.

diff --git a/clash-ghc/src-bin-861/Clash/Main.hs b/clash-ghc/src-bin-861/Clash/Main.hs
@@ -89,7 +89,7 @@ import           Data.IORef (IORef, newIORef, readIORef)
 import qualified Data.Version (showVersion)
 
 import qualified Clash.Backend
-import           Clash.Backend (AggressiveXOptBB, RenderEnums)
+import           Clash.Backend (AggressiveXOptBB, DomainMap, RenderEnums)
 import           Clash.Backend.SystemVerilog (SystemVerilogState)
 import           Clash.Backend.VHDL    (VHDLState)
 import           Clash.Backend.Verilog (VerilogState)
@@ -973,19 +973,19 @@ abiHash strs = do
 -----------------------------------------------------------------------------
 -- HDL Generation
 
-makeHDL' :: Clash.Backend.Backend backend => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> backend)
+makeHDL' :: Clash.Backend.Backend backend => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> backend)
          -> Ghc () -> IORef ClashOpts -> [(String,Maybe Phase)] -> Ghc ()
 makeHDL' _       _           _ []   = throwGhcException (CmdLineError "No input files")
 makeHDL' backend startAction r srcs = makeHDL backend startAction r $ fmap fst srcs
 
 makeVHDL :: Ghc () -> IORef ClashOpts -> [(String, Maybe Phase)] -> Ghc ()
-makeVHDL = makeHDL' (Clash.Backend.initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> VHDLState)
+makeVHDL = makeHDL' (Clash.Backend.initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> VHDLState)
 
 makeVerilog :: Ghc () -> IORef ClashOpts -> [(String, Maybe Phase)] -> Ghc ()
-makeVerilog = makeHDL' (Clash.Backend.initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> VerilogState)
+makeVerilog = makeHDL' (Clash.Backend.initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> VerilogState)
 
 makeSystemVerilog :: Ghc () -> IORef ClashOpts -> [(String, Maybe Phase)] -> Ghc ()
-makeSystemVerilog = makeHDL' (Clash.Backend.initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> SystemVerilogState)
+makeSystemVerilog = makeHDL' (Clash.Backend.initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> SystemVerilogState)
 
 -- -----------------------------------------------------------------------------
 -- Util

diff --git a/clash-ghc/src-bin-881/Clash/GHCi/UI.hs b/clash-ghc/src-bin-881/Clash/GHCi/UI.hs
@@ -143,7 +143,7 @@ import Clash.GHCi.Leak
 
 -- clash additions
 import qualified Clash.Backend
-import           Clash.Backend (AggressiveXOptBB, RenderEnums)
+import           Clash.Backend (AggressiveXOptBB, DomainMap, RenderEnums, emptyDomainMap)
 import           Clash.Backend.SystemVerilog (SystemVerilogState)
 import           Clash.Backend.VHDL (VHDLState)
 import           Clash.Backend.Verilog (VerilogState)
@@ -2065,7 +2065,7 @@ exceptT :: Applicative m => Either e a -> ExceptT e m a
 exceptT = ExceptT . pure
 
 makeHDL' :: Clash.Backend.Backend backend
-         => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> backend)
+         => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> backend)
          -> IORef ClashOpts
          -> [FilePath]
          -> InputT GHCi ()
@@ -2106,7 +2106,7 @@ makeHDL' backend opts lst = go =<< case lst of
 
 makeHDL :: GHC.GhcMonad m
         => Clash.Backend.Backend backend
-        => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> backend)
+        => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> backend)
         -> Ghc ()
         -> IORef ClashOpts
         -> [FilePath]
@@ -2125,7 +2125,7 @@ makeHDL backend startAction optsRef srcs = do
                   frcUdf = opt_forceUndefined opts1
                   xOptBB = opt_aggressiveXOptBB opts1
                   enums  = opt_renderEnums opts1
-                  hdl    = Clash.Backend.hdlKind backend'
+                  hdl    = Clash.Backend.hdlKind backendE
                   -- determine whether `-outputdir` was used
                   outputDir = do odir <- objectDir dflags
                                  hidir <- hiDir dflags
@@ -2138,11 +2138,12 @@ makeHDL backend startAction optsRef srcs = do
                   opts2 = opts1 { opt_hdlDir = maybe outputDir Just (opt_hdlDir opts1)
                                 , opt_importPaths = idirs}
                   backend' = backend iw syn esc lw frcUdf (coerce xOptBB) (coerce enums)
+                  backendE = backend' emptyDomainMap
 
               checkMonoLocalBinds dflags
               checkImportDirs opts0 idirs
 
-              primDirs <- Clash.Backend.primDirs backend'
+              primDirs <- Clash.Backend.primDirs backendE
 
               forM_ srcs $ \src -> do
                 -- Generate bindings:
@@ -2161,7 +2162,7 @@ makeHDL backend startAction optsRef srcs = do
                   (buildCustomReprs reprs)
                   domainConfs
                   bindingsMap
-                  (Just backend')
+                  (Just (backend' domainConfs))
                   primMap
                   tcm
                   tupTcm

diff --git a/clash-ghc/src-bin-881/Clash/Main.hs b/clash-ghc/src-bin-881/Clash/Main.hs
@@ -86,7 +86,7 @@ import           Data.IORef (IORef, newIORef, readIORef)
 import qualified Data.Version (showVersion)
 
 import qualified Clash.Backend
-import           Clash.Backend (AggressiveXOptBB, RenderEnums)
+import           Clash.Backend (AggressiveXOptBB, DomainMap, RenderEnums)
 import           Clash.Backend.SystemVerilog (SystemVerilogState)
 import           Clash.Backend.VHDL    (VHDLState)
 import           Clash.Backend.Verilog (VerilogState)
@@ -982,7 +982,7 @@ abiHash strs = do
 
 makeHDL'
   :: Clash.Backend.Backend backend
-  => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> backend)
+  => (Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> backend)
   -> Ghc () -> IORef ClashOpts -> [(String,Maybe Phase)] -> Ghc ()
 makeHDL' _       _           _ []   = throwGhcException (CmdLineError "No input files")
 makeHDL' backend startAction r srcs = makeHDL backend startAction r $ fmap fst srcs